]> asedeno.scripts.mit.edu Git - linux.git/commit
ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk
authorGeorge Cherian <george.cherian@ti.com>
Fri, 2 May 2014 06:32:03 +0000 (12:02 +0530)
committerDavid S. Miller <davem@davemloft.net>
Mon, 5 May 2014 17:18:50 +0000 (13:18 -0400)
commitf9786f419d58fc6667ba07a5590640112b31ba64
treeb9aae203f04a1a47dba68073f590424e1c60c4f9
parent09c5537246fd469625d116080ab1caa72d170d96
ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clk

cpsw_cpts_rft_clk has got the choice of 3 clocksources
 -dpll_core_m4_ck
 -dpll_core_m5_ck
 -dpll_disp_m2_ck

By default dpll_core_m4_ck is selected, witn this as clock
source the CPTS doesnot work properly. It gives clockcheck errors
while running PTP.

 clockcheck: clock jumped backward or running slower than expected!

By selecting dpll_core_m5_ck as the clocksource fixes this issue.
In AM335x dpll_core_m5_ck is the default clocksource.

Signed-off-by: George Cherian <george.cherian@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/clk/ti/clk-43xx.c