]> asedeno.scripts.mit.edu Git - linux.git/commit
Merge branch 'clk-renesas' into clk-next
authorStephen Boyd <sboyd@kernel.org>
Thu, 18 Oct 2018 22:38:51 +0000 (15:38 -0700)
committerStephen Boyd <sboyd@kernel.org>
Thu, 18 Oct 2018 22:38:51 +0000 (15:38 -0700)
commitfaff3d8e852b1450e0e8e8f60c4e9af98549548a
treefc3bc8e7185cc19447cba54e23e6b476f6665ba9
parent9710ee14bec9a7ffa385342ffb03f91d274b3d07
parentbe783cc8d72bb1e48b50c1838a3afeafad4c91c7
Merge branch 'clk-renesas' into clk-next

* clk-renesas: (36 commits)
  clk: renesas: r7s9210: Add SPI clocks
  clk: renesas: r7s9210: Move table update to separate function
  clk: renesas: r7s9210: Convert some clocks to early
  clk: renesas: cpg-mssr: Add early clock support
  clk: renesas: r8a77970: Add TPU clock
  clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
  clk: renesas: cpg-mssr: Add r8a774c0 support
  clk: renesas: Add r8a774c0 CPG Core Clock Definitions
  clk: renesas: r8a7743: Add r8a7744 support
  clk: renesas: Add r8a7744 CPG Core Clock Definitions
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
  dt-bindings: clock: renesas: Convert to SPDX identifiers
  clk: renesas: cpg-mssr: Add R7S9210 support
  clk: renesas: r8a77970: Add TMU clocks
  clk: renesas: r8a77970: Add CMT clocks
  clk: renesas: r9a06g032: Fix UART34567 clock rate
  clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
  clk: renesas: r8a77980: Add CMT clocks
  clk: renesas: r8a77990: Add missing I2C7 clock
  ...
drivers/clk/renesas/Kconfig
drivers/clk/renesas/r8a7743-cpg-mssr.c
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/r8a77970-cpg-mssr.c
drivers/clk/renesas/r8a77995-cpg-mssr.c
drivers/clk/renesas/rcar-gen3-cpg.c
drivers/clk/renesas/rcar-gen3-cpg.h
drivers/clk/renesas/renesas-cpg-mssr.c
drivers/clk/renesas/renesas-cpg-mssr.h