It seems that on i.MX8MQ the power domain controller does not propagate
resets to the VPU cores on resume. Add a callback to allow implementing
manual reset of the VPU cores after ungating the power domain.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* @codec: Supported codecs
* @codec_ops: Codec ops.
* @init: Initialize hardware.
* @codec: Supported codecs
* @codec_ops: Codec ops.
* @init: Initialize hardware.
+ * @runtime_resume: reenable hardware after power gating
* @vepu_irq: encoder interrupt handler
* @vdpu_irq: decoder interrupt handler
* @clk_names: array of clock names
* @vepu_irq: encoder interrupt handler
* @vdpu_irq: decoder interrupt handler
* @clk_names: array of clock names
unsigned int codec;
const struct hantro_codec_ops *codec_ops;
int (*init)(struct hantro_dev *vpu);
unsigned int codec;
const struct hantro_codec_ops *codec_ops;
int (*init)(struct hantro_dev *vpu);
+ int (*runtime_resume)(struct hantro_dev *vpu);
irqreturn_t (*vepu_irq)(int irq, void *priv);
irqreturn_t (*vdpu_irq)(int irq, void *priv);
const char *clk_names[HANTRO_MAX_CLOCKS];
irqreturn_t (*vepu_irq)(int irq, void *priv);
irqreturn_t (*vdpu_irq)(int irq, void *priv);
const char *clk_names[HANTRO_MAX_CLOCKS];
+#ifdef CONFIG_PM
+static int hantro_runtime_resume(struct device *dev)
+{
+ struct hantro_dev *vpu = dev_get_drvdata(dev);
+
+ if (vpu->variant->runtime_resume)
+ return vpu->variant->runtime_resume(vpu);
+
+ return 0;
+}
+#endif
+
static const struct dev_pm_ops hantro_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
static const struct dev_pm_ops hantro_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
};
static struct platform_driver hantro_driver = {
};
static struct platform_driver hantro_driver = {