Merge branch 'stmmac-Add-EHL-and-TGL-PCI-info-and-PCI-ID'

Voon Weifeng says:

====================
stmmac: Add EHL and TGL PCI info and PCI ID

In order to keep PCI info simple and neat, this patch series have
introduced a 3 hierarchy of struct. First layer will be the
intel_mgbe_common_data struct which keeps all Intel common configuration.
Second layer will be xxx_common_data which keeps all the different Intel
microarchitecture, e.g tgl, ehl. The third layer will be configuration
that tied to the PCI ID only based on speed and RGMII/SGMII interface.

EHL and TGL will also having a higher system clock which is 200Mhz.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
index d5d08e11c35378121b638e0aade35b2a38cee2fe..20906287b6d465a921b5d2c886d6aeb4d82cdb46 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
@@ -9,6 +9,7 @@
   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *******************************************************************************/
 
+#include <linux/clk-provider.h>
 #include <linux/pci.h>
 #include <linux/dmi.h>
 
@@ -108,6 +109,166 @@ static const struct stmmac_pci_info stmmac_pci_info = {
        .setup = stmmac_default_data,
 };
 
+static int intel_mgbe_common_data(struct pci_dev *pdev,
+                                 struct plat_stmmacenet_data *plat)
+{
+       int i;
+
+       plat->clk_csr = 5;
+       plat->has_gmac = 0;
+       plat->has_gmac4 = 1;
+       plat->force_sf_dma_mode = 0;
+       plat->tso_en = 1;
+
+       plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
+
+       for (i = 0; i < plat->rx_queues_to_use; i++) {
+               plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
+               plat->rx_queues_cfg[i].chan = i;
+
+               /* Disable Priority config by default */
+               plat->rx_queues_cfg[i].use_prio = false;
+
+               /* Disable RX queues routing by default */
+               plat->rx_queues_cfg[i].pkt_route = 0x0;
+       }
+
+       for (i = 0; i < plat->tx_queues_to_use; i++) {
+               plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
+
+               /* Disable Priority config by default */
+               plat->tx_queues_cfg[i].use_prio = false;
+       }
+
+       /* FIFO size is 4096 bytes for 1 tx/rx queue */
+       plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
+       plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
+
+       plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
+       plat->tx_queues_cfg[0].weight = 0x09;
+       plat->tx_queues_cfg[1].weight = 0x0A;
+       plat->tx_queues_cfg[2].weight = 0x0B;
+       plat->tx_queues_cfg[3].weight = 0x0C;
+       plat->tx_queues_cfg[4].weight = 0x0D;
+       plat->tx_queues_cfg[5].weight = 0x0E;
+       plat->tx_queues_cfg[6].weight = 0x0F;
+       plat->tx_queues_cfg[7].weight = 0x10;
+
+       plat->mdio_bus_data->phy_mask = 0;
+
+       plat->dma_cfg->pbl = 32;
+       plat->dma_cfg->pblx8 = true;
+       plat->dma_cfg->fixed_burst = 0;
+       plat->dma_cfg->mixed_burst = 0;
+       plat->dma_cfg->aal = 0;
+
+       plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
+                                GFP_KERNEL);
+       if (!plat->axi)
+               return -ENOMEM;
+
+       plat->axi->axi_lpi_en = 0;
+       plat->axi->axi_xit_frm = 0;
+       plat->axi->axi_wr_osr_lmt = 1;
+       plat->axi->axi_rd_osr_lmt = 1;
+       plat->axi->axi_blen[0] = 4;
+       plat->axi->axi_blen[1] = 8;
+       plat->axi->axi_blen[2] = 16;
+
+       plat->ptp_max_adj = plat->clk_ptp_rate;
+
+       /* Set system clock */
+       plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
+                                                  "stmmac-clk", NULL, 0,
+                                                  plat->clk_ptp_rate);
+
+       if (IS_ERR(plat->stmmac_clk)) {
+               dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
+               plat->stmmac_clk = NULL;
+       }
+       clk_prepare_enable(plat->stmmac_clk);
+
+       /* Set default value for multicast hash bins */
+       plat->multicast_filter_bins = HASH_TABLE_SIZE;
+
+       /* Set default value for unicast filter entries */
+       plat->unicast_filter_entries = 1;
+
+       /* Set the maxmtu to a default of JUMBO_LEN */
+       plat->maxmtu = JUMBO_LEN;
+
+       return 0;
+}
+
+static int ehl_common_data(struct pci_dev *pdev,
+                          struct plat_stmmacenet_data *plat)
+{
+       int ret;
+
+       plat->rx_queues_to_use = 8;
+       plat->tx_queues_to_use = 8;
+       plat->clk_ptp_rate = 200000000;
+       ret = intel_mgbe_common_data(pdev, plat);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int ehl_sgmii_data(struct pci_dev *pdev,
+                         struct plat_stmmacenet_data *plat)
+{
+       plat->bus_id = 1;
+       plat->phy_addr = 0;
+       plat->interface = PHY_INTERFACE_MODE_SGMII;
+       return ehl_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
+       .setup = ehl_sgmii_data,
+};
+
+static int ehl_rgmii_data(struct pci_dev *pdev,
+                         struct plat_stmmacenet_data *plat)
+{
+       plat->bus_id = 1;
+       plat->phy_addr = 0;
+       plat->interface = PHY_INTERFACE_MODE_RGMII;
+       return ehl_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
+       .setup = ehl_rgmii_data,
+};
+
+static int tgl_common_data(struct pci_dev *pdev,
+                          struct plat_stmmacenet_data *plat)
+{
+       int ret;
+
+       plat->rx_queues_to_use = 6;
+       plat->tx_queues_to_use = 4;
+       plat->clk_ptp_rate = 200000000;
+       ret = intel_mgbe_common_data(pdev, plat);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int tgl_sgmii_data(struct pci_dev *pdev,
+                         struct plat_stmmacenet_data *plat)
+{
+       plat->bus_id = 1;
+       plat->phy_addr = 0;
+       plat->interface = PHY_INTERFACE_MODE_SGMII;
+       return tgl_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
+       .setup = tgl_sgmii_data,
+};
+
 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
        {
                .func = 6,
@@ -293,10 +454,15 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
  */
 static void stmmac_pci_remove(struct pci_dev *pdev)
 {
+       struct net_device *ndev = dev_get_drvdata(&pdev->dev);
+       struct stmmac_priv *priv = netdev_priv(ndev);
        int i;
 
        stmmac_dvr_remove(&pdev->dev);
 
+       if (priv->plat->stmmac_clk)
+               clk_unregister_fixed_rate(priv->plat->stmmac_clk);
+
        for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
                if (pci_resource_len(pdev, i) == 0)
                        continue;
@@ -349,6 +515,9 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
 
 #define STMMAC_QUARK_ID  0x0937
 #define STMMAC_DEVICE_ID 0x1108
+#define STMMAC_EHL_RGMII1G_ID  0x4b30
+#define STMMAC_EHL_SGMII1G_ID  0x4b31
+#define STMMAC_TGL_SGMII1G_ID  0xa0ac
 
 #define STMMAC_DEVICE(vendor_id, dev_id, info) {       \
        PCI_VDEVICE(vendor_id, dev_id),                 \
@@ -359,6 +528,9 @@ static const struct pci_device_id stmmac_id_table[] = {
        STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info),
        STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info),
        STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info),
+       STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info),
+       STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info),
+       STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info),
        {}
 };
 

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
index c48224973a374577a1d196ac71ffed1d25f776d3..173493db038c0a9f5199bf1675429e0b379a6b4f 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
@@ -194,6 +194,9 @@ void stmmac_ptp_register(struct stmmac_priv *priv)
                priv->pps[i].available = true;
        }
 
+       if (priv->plat->ptp_max_adj)
+               stmmac_ptp_clock_ops.max_adj = priv->plat->ptp_max_adj;
+
        stmmac_ptp_clock_ops.n_per_out = priv->dma_cap.pps_out_num;
 
        spin_lock_init(&priv->ptp_lock);

diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 5cc6b6faf35913924aea4950aefd2a8a75262bcc..7ad7ae35cf88a884815aeea662c241dff8106f8c 100644 (file)
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -168,6 +168,7 @@ struct plat_stmmacenet_data {
        struct clk *clk_ptp_ref;
        unsigned int clk_ptp_rate;
        unsigned int clk_ref_rate;
+       s32 ptp_max_adj;
        struct reset_control *stmmac_rst;
        struct stmmac_axi *axi;
        int has_gmac4;