]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: change Vega IH ring 1 config
authorChristian König <christian.koenig@amd.com>
Wed, 27 Feb 2019 13:54:23 +0000 (14:54 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 19 Mar 2019 20:36:58 +0000 (15:36 -0500)
Disable overflow and enable full drain. This makes fault handling on ring 1
much more reliable since we don't generate back pressure any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/vega10_ih.c

index 6d1f804277f84b224b4999e82e0a12913e70014b..d4a3cc413af88b0204d87dc92a4cb9505a479289 100644 (file)
@@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 
                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
                ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+               ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                          WPTR_OVERFLOW_ENABLE, 0);
+               ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                          RB_FULL_DRAIN_ENABLE, 1);
                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
 
                /* set rptr, wptr to 0 */