reg = <0x100440A0 0x20>;
#power-domain-cells = <0>;
label = "DISP1";
- clocks = <&clock CLK_FIN_PLL>,
- <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
- <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
- clock-names = "oscclk", "clk0", "clk1";
};
pd_mau: power-domain@100440c0 {
reg = <0x10044000 0x20>;
#power-domain-cells = <0>;
label = "GSC";
- clocks = <&clock CLK_FIN_PLL>,
- <&clock CLK_MOUT_USER_ACLK300_GSCL>,
- <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
- clock-names = "oscclk", "clk0", "asb0", "asb1";
};
isp_pd: power-domain@10044020 {
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
- clocks = <&clock CLK_FIN_PLL>,
- <&clock CLK_MOUT_USER_ACLK333>,
- <&clock CLK_ACLK333>;
- clock-names = "oscclk", "clk0","asb0";
#power-domain-cells = <0>;
label = "MFC";
};
reg = <0x100440C0 0x20>;
#power-domain-cells = <0>;
label = "DISP";
- clocks = <&clock CLK_FIN_PLL>,
- <&clock CLK_MOUT_USER_ACLK200_DISP1>,
- <&clock CLK_MOUT_USER_ACLK300_DISP1>,
- <&clock CLK_MOUT_USER_ACLK400_DISP1>,
- <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
- clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
mau_pd: power-domain@100440e0 {