dt-bindings: net: dsa: Add documentation for NXP SJA1105 driver

Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/Documentation/devicetree/bindings/net/dsa/sja1105.txt b/Documentation/devicetree/bindings/net/dsa/sja1105.txt
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+NXP SJA1105 switch driver
+=========================
+
+Required properties:
+
+- compatible:
+       Must be one of:
+       - "nxp,sja1105e"
+       - "nxp,sja1105t"
+       - "nxp,sja1105p"
+       - "nxp,sja1105q"
+       - "nxp,sja1105r"
+       - "nxp,sja1105s"
+
+       Although the device ID could be detected at runtime, explicit bindings
+       are required in order to be able to statically check their validity.
+       For example, SGMII can only be specified on port 4 of R and S devices,
+       and the non-SGMII devices, while pin-compatible, are not equal in terms
+       of support for RGMII internal delays (supported on P/Q/R/S, but not on
+       E/T).
+
+Optional properties:
+
+- sja1105,role-mac:
+- sja1105,role-phy:
+       Boolean properties that can be assigned under each port node. By
+       default (unless otherwise specified) a port is configured as MAC if it
+       is driving a PHY (phy-handle is present) or as PHY if it is PHY-less
+       (fixed-link specified, presumably because it is connected to a MAC).
+       The effect of this property (in either its implicit or explicit form)
+       is:
+       - In the case of MII or RMII it specifies whether the SJA1105 port is a
+         clock source or sink for this interface (not applicable for RGMII
+         where there is a Tx and an Rx clock).
+       - In the case of RGMII it affects the behavior regarding internal
+         delays:
+         1. If sja1105,role-mac is specified, and the phy-mode property is one
+            of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity
+            designated to apply the delay/clock skew necessary for RGMII
+            is the PHY. The SJA1105 MAC does not apply any internal delays.
+         2. If sja1105,role-phy is specified, and the phy-mode property is one
+            of the above, the designated entity to apply the internal delays
+            is the SJA1105 MAC (if hardware-supported). This is only supported
+            by the second-generation (P/Q/R/S) hardware. On a first-generation
+            E or T device, it is an error to specify an RGMII phy-mode other
+            than "rgmii" for a port that is in fixed-link mode. In that case,
+            the clock skew must either be added by the MAC at the other end of
+            the fixed-link, or by PCB serpentine traces on the board.
+       These properties are required, for example, in the case where SJA1105
+       ports are at both ends of a MII/RMII PHY-less setup. One end would need
+       to have sja1105,role-mac, while the other sja1105,role-phy.
+
+See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard
+DSA required and optional properties.
+
+Other observations
+------------------
+
+The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least
+one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
+cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
+depends on the SPI bus master driver.
+
+Example
+-------
+
+Ethernet switch connected via SPI to the host, CPU port wired to enet2:
+
+arch/arm/boot/dts/ls1021a-tsn.dts:
+
+/* SPI controller of the LS1021 */
+&dspi0 {
+       sja1105@1 {
+               reg = <0x1>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "nxp,sja1105t";
+               spi-max-frequency = <4000000>;
+               fsl,spi-cs-sck-delay = <1000>;
+               fsl,spi-sck-cs-delay = <1000>;
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       port@0 {
+                               /* ETH5 written on chassis */
+                               label = "swp5";
+                               phy-handle = <&rgmii_phy6>;
+                               phy-mode = "rgmii-id";
+                               reg = <0>;
+                               /* Implicit "sja1105,role-mac;" */
+                       };
+                       port@1 {
+                               /* ETH2 written on chassis */
+                               label = "swp2";
+                               phy-handle = <&rgmii_phy3>;
+                               phy-mode = "rgmii-id";
+                               reg = <1>;
+                               /* Implicit "sja1105,role-mac;" */
+                       };
+                       port@2 {
+                               /* ETH3 written on chassis */
+                               label = "swp3";
+                               phy-handle = <&rgmii_phy4>;
+                               phy-mode = "rgmii-id";
+                               reg = <2>;
+                               /* Implicit "sja1105,role-mac;" */
+                       };
+                       port@3 {
+                               /* ETH4 written on chassis */
+                               phy-handle = <&rgmii_phy5>;
+                               label = "swp4";
+                               phy-mode = "rgmii-id";
+                               reg = <3>;
+                               /* Implicit "sja1105,role-mac;" */
+                       };
+                       port@4 {
+                               /* Internal port connected to eth2 */
+                               ethernet = <&enet2>;
+                               phy-mode = "rgmii";
+                               reg = <4>;
+                               /* Implicit "sja1105,role-phy;" */
+                               fixed-link {
+                                       speed = <1000>;
+                                       full-duplex;
+                               };
+                       };
+               };
+       };
+};
+
+/* MDIO controller of the LS1021 */
+&mdio0 {
+       /* BCM5464 */
+       rgmii_phy3: ethernet-phy@3 {
+               reg = <0x3>;
+       };
+       rgmii_phy4: ethernet-phy@4 {
+               reg = <0x4>;
+       };
+       rgmii_phy5: ethernet-phy@5 {
+               reg = <0x5>;
+       };
+       rgmii_phy6: ethernet-phy@6 {
+               reg = <0x6>;
+       };
+};
+
+/* Ethernet master port of the LS1021 */
+&enet2 {
+       phy-connection-type = "rgmii";
+       status = "ok";
+       fixed-link {
+               speed = <1000>;
+               full-duplex;
+       };
+};