]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/i915: Always wake the device to flush the GTT
authorChris Wilson <chris@chris-wilson.co.uk>
Tue, 29 Aug 2017 19:25:46 +0000 (20:25 +0100)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 30 Aug 2017 19:08:14 +0000 (12:08 -0700)
Since we hold the device wakeref when writing through the GTT (otherwise
the writes would fail), we presumed that before the device sleeps those
writes would naturally be flushed and that we wouldn't need our mmio
read trick. However, that presumption seems false and a sleepy bxt seems
to require us to always manually flush the GTT writes prior to direct
access.

Fixes: e2a2aa36a509 ("drm/i915: Check we have an wake device before flushing GTT writes")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829192546.1087-1-chris@chris-wilson.co.uk
(cherry picked from commit b69a784f5e2308d6360a76eceae450e96751f3e4)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/i915_gem.c

index 9c62b18ca03a8bc127cda23b1ca30e051184421f..a54a9631f59e17c246cba644f54e5432a563a272 100644 (file)
@@ -695,12 +695,11 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
        switch (obj->base.write_domain) {
        case I915_GEM_DOMAIN_GTT:
                if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-                       if (intel_runtime_pm_get_if_in_use(dev_priv)) {
-                               spin_lock_irq(&dev_priv->uncore.lock);
-                               POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
-                               spin_unlock_irq(&dev_priv->uncore.lock);
-                               intel_runtime_pm_put(dev_priv);
-                       }
+                       intel_runtime_pm_get(dev_priv);
+                       spin_lock_irq(&dev_priv->uncore.lock);
+                       POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+                       spin_unlock_irq(&dev_priv->uncore.lock);
+                       intel_runtime_pm_put(dev_priv);
                }
 
                intel_fb_obj_flush(obj,