clk: renesas: r8a7743: Add r8a7744 support

Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
Reset support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 2edcb1bdb4872f0152f9e74376229f459eb3bb87..7a6ceecc213e0a1716e0099111b1fd198fafc823 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -6,7 +6,7 @@ config CLK_RENESAS
        select CLK_R7S9210 if ARCH_R7S9210
        select CLK_R8A73A4 if ARCH_R8A73A4
        select CLK_R8A7740 if ARCH_R8A7740
-       select CLK_R8A7743 if ARCH_R8A7743
+       select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
        select CLK_R8A7745 if ARCH_R8A7745
        select CLK_R8A77470 if ARCH_R8A77470
        select CLK_R8A774A1 if ARCH_R8A774A1

diff --git a/drivers/clk/renesas/r8a7743-cpg-mssr.c b/drivers/clk/renesas/r8a7743-cpg-mssr.c
index 011c170ec3f95d65f7a83384b42431bcbfc86e55..ab994f4c1ec8c62faa1b829f88cbd9cf5e490cbf 100644 (file)
--- a/drivers/clk/renesas/r8a7743-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7743-cpg-mssr.c
@@ -11,6 +11,7 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/of.h>
 #include <linux/soc/renesas/rcar-rst.h>
 
 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
@@ -37,7 +38,7 @@ enum clk_ids {
        MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
+static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
        /* External Clock Inputs */
        DEF_INPUT("extal",      CLK_EXTAL),
        DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
@@ -238,6 +239,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
 static int __init r8a7743_cpg_mssr_init(struct device *dev)
 {
        const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+       struct device_node *np = dev->of_node;
+       unsigned int i;
        u32 cpg_mode;
        int error;
 
@@ -247,6 +250,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev)
 
        cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 
+       if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
+               /* RZ/G1N uses a 1/5 divider for ZG */
+               for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
+                       if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
+                               r8a7743_core_clks[i].div = 5;
+                               break;
+                       }
+       }
        return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
 }
 

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index b97e0e3ff0b1d156eaa99e7f681278e920dc037b..c4beec7b563f26553549748205498473e998b281 100644 (file)
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -693,6 +693,11 @@ static const struct of_device_id cpg_mssr_match[] = {
                .compatible = "renesas,r8a7743-cpg-mssr",
                .data = &r8a7743_cpg_mssr_info,
        },
+       /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
+       {
+               .compatible = "renesas,r8a7744-cpg-mssr",
+               .data = &r8a7743_cpg_mssr_info,
+       },
 #endif
 #ifdef CONFIG_CLK_R8A7745
        {