PCI: designware: Check LTSSM training bit before deciding link is up

The link may be up but still in link training.  In this case, we can't
think the link is up and operating correctly.  Teach dw_pcie_link_up() to
be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.

Also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that it's consistent
with other macros.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 44c63fb6b1cf3359519b6c2916fa6eb42495d126..085fde272594baada9c0608ab0a70b085f94eb8a 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -98,7 +98,8 @@
 /* PCIe Port Logic registers */
 #define PLR_OFFSET                     0x700
 #define PCIE_PHY_DEBUG_R1              (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP      0x00000010
+#define PCIE_PHY_DEBUG_R1_LINK_UP      (0x1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING     (0x1 << 29)
 
 static struct pci_ops dw_pcie_ops;
 
@@ -491,7 +492,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
                return pp->ops->link_up(pp);
 
        val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
-       return val & PCIE_PHY_DEBUG_R1_LINK_UP;
+       return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+               (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
 }
 
 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,