drm/i915/icl: Prepare for more rings

Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.

Bspec: 7021

v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
  - Update for POR changes. (Daniele Ceraolo Spurio)
  - Add provisional guc engine ids - to be checked and confirmed.
v7:
  - Rebased.
  - Added the new ring masks.
  - Added the new HW ids.
v8:
  - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)

v9: increase MAX_ENGINE_INSTANCE to 3

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180228101153.7224-1-mika.kuoppala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7bbec5546d12f1b7edac53a53f73615decc04129..10c9e5e619ab86518d28ab7102ad7a85c293671a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2746,6 +2746,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define BLT_RING       ENGINE_MASK(BCS)
 #define VEBOX_RING     ENGINE_MASK(VECS)
 #define BSD2_RING      ENGINE_MASK(VCS2)
+#define BSD3_RING      ENGINE_MASK(VCS3)
+#define BSD4_RING      ENGINE_MASK(VCS4)
+#define VEBOX2_RING    ENGINE_MASK(VECS2)
 #define ALL_ENGINES    (~0)
 
 #define HAS_ENGINE(dev_priv, id) \

diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index d9f0709973d11d58a59adc7f452064190056343f..f54c4ff74dedf3c914b41b20baae111b1515160a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -57,6 +57,6 @@
 #define GEM_TRACE(...) do { } while (0)
 #endif
 
-#define I915_NUM_ENGINES 5
+#define I915_NUM_ENGINES 8
 
 #endif /* __I915_GEM_H__ */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea5b2c537d4f62f700cf5828ce84bb7045d403b..95a2e51ecbb0885a8aa98440d694239c377372b6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BCS_HW         2
 #define VECS_HW                3
 #define VCS2_HW                4
+#define VCS3_HW                6
+#define VCS4_HW                7
+#define VECS2_HW       12
 
 /* Engine class */
 
@@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define OTHER_CLASS            4
 #define MAX_ENGINE_CLASS       4
 
-#define MAX_ENGINE_INSTANCE    1
+#define MAX_ENGINE_INSTANCE    3
 
 /* PCI config space */
 

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1c780cc4cd482b9d6dc23553b9225235503dafa0..cadc5f81ed728a93e7679ff7b32631b67c705b1f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -542,6 +542,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
                info->num_scalers[PIPE_C] = 1;
        }
 
+       BUILD_BUG_ON(I915_NUM_ENGINES >
+                    sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
+
        /*
         * Skylake and Broxton currently don't expose the topmost plane as its
         * use is exclusive with the legacy cursor and we only want to expose

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8904ad87bf378798f59ea050b848703484a3724a..ab5bfd305477aa94ed3653c877732268e12c9d69 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,8 @@ struct sseu_dev_info {
        u8 has_eu_pg:1;
 };
 
+typedef u8 intel_ring_mask_t;
+
 struct intel_device_info {
        u16 device_id;
        u16 gen_mask;
@@ -132,7 +134,7 @@ struct intel_device_info {
        u8 gen;
        u8 gt; /* GT number, 0 if undefined */
        u8 num_rings;
-       u8 ring_mask; /* Rings supported by the HW */
+       intel_ring_mask_t ring_mask; /* Rings supported by the HW */
 
        enum intel_platform platform;
        u32 platform_mask;

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index bbacf4d0f4cb56a6a1c74cf57e22098b4ad49f6d..90e4380cbdd5e30fa18df20455cc5b0d97694320 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -160,6 +160,9 @@ struct i915_ctx_workarounds {
 
 struct i915_request;
 
+#define I915_MAX_VCS   4
+#define I915_MAX_VECS  2
+
 /*
  * Engine IDs definitions.
  * Keep instances of the same type engine together.
@@ -169,8 +172,12 @@ enum intel_engine_id {
        BCS,
        VCS,
        VCS2,
+       VCS3,
+       VCS4,
 #define _VCS(n) (VCS + (n))
-       VECS
+       VECS,
+       VECS2
+#define _VECS(n) (VECS + (n))
 };
 
 struct i915_priolist {