drm/amdgpu: correct smu rlc handshake enablement bit

Correct the enablement bit of SMU RLC handshake.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index db8c7fbc1b5fa09b6bd62408650f876c13d9cd7c..ec71e2a7d7b71c0af24f9e0a6f2818b3c5b06029 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1779,9 +1779,9 @@ static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
                 * hence no handshake between SMU & RLC
                 * GFXOFF will be disabled
                 */
-               rlc_pg_cntl |= 0x80000;
+               rlc_pg_cntl |= 0x800000;
        } else
-               rlc_pg_cntl &= ~0x80000;
+               rlc_pg_cntl &= ~0x800000;
        WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
 }