arm64: dts: imx8mm: Move usdhc clocks assignment to board DT

usdhc's clock rate is different according to different devices
connected, so clock rate assignment should be placed in board
DT according to different devices connected on each usdhc port.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 5c3b23c4f91f54c27c232dd7b00320fab9949c56..28ab17a277bb92a193380db6dff3626c0719b169 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -295,6 +295,8 @@ usb1_drd_sw: endpoint {
 };
 
 &usdhc2 {
+       assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+       assigned-clock-rates = <200000000>;
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
        pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -306,6 +308,8 @@ &usdhc2 {
 };
 
 &usdhc3 {
+       assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+       assigned-clock-rates = <400000000>;
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 7f4291aa36c654b901066f997a14dad26077e2fe..93f2e620d70a5de2e943c5b15134022c305d5c99 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -702,8 +702,6 @@ usdhc1: mmc@30b40000 {
                                         <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
                                         <&clk IMX8MM_CLK_USDHC1_ROOT>;
                                clock-names = "ipg", "ahb", "per";
-                               assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
-                               assigned-clock-rates = <400000000>;
                                fsl,tuning-start-tap = <20>;
                                fsl,tuning-step= <2>;
                                bus-width = <4>;
@@ -732,8 +730,6 @@ usdhc3: mmc@30b60000 {
                                         <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
                                         <&clk IMX8MM_CLK_USDHC3_ROOT>;
                                clock-names = "ipg", "ahb", "per";
-                               assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
-                               assigned-clock-rates = <400000000>;
                                fsl,tuning-start-tap = <20>;
                                fsl,tuning-step= <2>;
                                bus-width = <4>;