ARM: dts: am33xx: add clkctrl nodes

Add clkctrl nodes for AM33xx SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 48a15fc641f22e40301c505625fc331efc4610e9..e67b4d65c8d09e69b5162481f323d78ca9a7cac0 100644 (file)
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -409,6 +409,6 @@ &sham {
 };
 
 &rtc {
-       clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+       clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
        clock-names = "ext-clk", "int-clk";
 };

diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index cdc1b2be792f3665d8d17bec7c5b52617ef85a52..d5be9fc4f416816c004041f4b146da1b79197b20 100644 (file)
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -446,7 +446,7 @@ &sham {
 
 &rtc {
        system-power-controller;
-       clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+       clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
        clock-names = "ext-clk", "int-clk";
 };
 

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index ddd897556e035b6306306ca33eccc65c7ed45e3b..fee6b3ee17412638a9ac67d29f9773dd22100c95 100644 (file)
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -790,6 +790,6 @@ &dcan1 {
 };
 
 &rtc {
-       clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+       clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
        clock-names = "ext-clk", "int-clk";
 };

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 9ba4b18c0cb21711dcd8ef60648a0916914819e7..fa608cd5dc14dcc6d1101c6675d54ed4c1206ee6 100644 (file)
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -722,6 +722,6 @@ &lcdc {
 };
 
 &rtc {
-       clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+       clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
        clock-names = "ext-clk", "int-clk";
 };

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 8d8319590cde7353ce46a4bd9e21f580d5d7ae9b..95d5c9d136c5b2f5e318fc00fbfc0cf425c8e004 100644 (file)
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -292,14 +292,6 @@ dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
                clock-div = <4>;
        };
 
-       cefuse_fck: cefuse_fck@a20 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&sys_clkin_ck>;
-               ti,bit-shift = <1>;
-               reg = <0x0a20>;
-       };
-
        clk_24mhz: clk_24mhz {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
@@ -316,14 +308,6 @@ clkdiv32k_ck: clkdiv32k_ck {
                clock-div = <732>;
        };
 
-       clkdiv32k_ick: clkdiv32k_ick@14c {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ck>;
-               ti,bit-shift = <1>;
-               reg = <0x014c>;
-       };
-
        l3_gclk: l3_gclk {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
@@ -350,49 +334,49 @@ mmu_fck: mmu_fck@914 {
        timer1_fck: timer1_fck@528 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+               clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
                reg = <0x0528>;
        };
 
        timer2_fck: timer2_fck@508 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0508>;
        };
 
        timer3_fck: timer3_fck@50c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x050c>;
        };
 
        timer4_fck: timer4_fck@510 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0510>;
        };
 
        timer5_fck: timer5_fck@518 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0518>;
        };
 
        timer6_fck: timer6_fck@51c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x051c>;
        };
 
        timer7_fck: timer7_fck@504 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0504>;
        };
 
@@ -423,7 +407,7 @@ ieee5000_fck: ieee5000_fck@e4 {
        wdt1_fck: wdt1_fck@538 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+               clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x0538>;
        };
 
@@ -493,42 +477,10 @@ cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                reg = <0x053c>;
        };
 
-       gpio0_dbclk: gpio0_dbclk@408 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&gpio0_dbclk_mux_ck>;
-               ti,bit-shift = <18>;
-               reg = <0x0408>;
-       };
-
-       gpio1_dbclk: gpio1_dbclk@ac {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00ac>;
-       };
-
-       gpio2_dbclk: gpio2_dbclk@b0 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00b0>;
-       };
-
-       gpio3_dbclk: gpio3_dbclk@b4 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&clkdiv32k_ick>;
-               ti,bit-shift = <18>;
-               reg = <0x00b4>;
-       };
-
        lcd_gclk: lcd_gclk@534 {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
@@ -577,58 +529,6 @@ clkout2_div_ck: clkout2_div_ck@700 {
                reg = <0x0700>;
        };
 
-       dbg_sysclk_ck: dbg_sysclk_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&sys_clkin_ck>;
-               ti,bit-shift = <19>;
-               reg = <0x0414>;
-       };
-
-       dbg_clka_ck: dbg_clka_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,gate-clock";
-               clocks = <&dpll_core_m4_ck>;
-               ti,bit-shift = <30>;
-               reg = <0x0414>;
-       };
-
-       stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-               ti,bit-shift = <22>;
-               reg = <0x0414>;
-       };
-
-       trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
-               ti,bit-shift = <20>;
-               reg = <0x0414>;
-       };
-
-       stm_clk_div_ck: stm_clk_div_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&stm_pmd_clock_mux_ck>;
-               ti,bit-shift = <27>;
-               ti,max-div = <64>;
-               reg = <0x0414>;
-               ti,index-power-of-two;
-       };
-
-       trace_clk_div_ck: trace_clk_div_ck@414 {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&trace_pmd_clk_mux_ck>;
-               ti,bit-shift = <24>;
-               ti,max-div = <64>;
-               reg = <0x0414>;
-               ti,index-power-of-two;
-       };
-
        clkout2_ck: clkout2_ck@700 {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
@@ -638,9 +538,88 @@ clkout2_ck: clkout2_ck@700 {
        };
 };
 
-&prcm_clockdomains {
-       clk_24mhz_clkdm: clk_24mhz_clkdm {
-               compatible = "ti,clockdomain";
-               clocks = <&clkdiv32k_ick>;
+&prcm {
+       l4_per_cm: l4_per_cm@0 {
+               compatible = "ti,omap4-cm";
+               reg = <0x0 0x200>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x0 0x200>;
+
+               l4_per_clkctrl: clk@14 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x14 0x13c>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_wkup_cm: l4_wkup_cm@400 {
+               compatible = "ti,omap4-cm";
+               reg = <0x400 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x400 0x100>;
+
+               l4_wkup_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0xd4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       mpu_cm: mpu_cm@600 {
+               compatible = "ti,omap4-cm";
+               reg = <0x600 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x600 0x100>;
+
+               mpu_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_rtc_cm: l4_rtc_cm@800 {
+               compatible = "ti,omap4-cm";
+               reg = <0x800 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x800 0x100>;
+
+               l4_rtc_clkctrl: clk@0 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x0 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       gfx_l3_cm: gfx_l3_cm@900 {
+               compatible = "ti,omap4-cm";
+               reg = <0x900 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x900 0x100>;
+
+               gfx_l3_clkctrl: clk@4 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x4 0x4>;
+                       #clock-cells = <2>;
+               };
+       };
+
+       l4_cefuse_cm: l4_cefuse_cm@a00 {
+               compatible = "ti,omap4-cm";
+               reg = <0xa00 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xa00 0x100>;
+
+               l4_cefuse_clkctrl: clk@20 {
+                       compatible = "ti,clkctrl";
+                       reg = <0x20 0x4>;
+                       #clock-cells = <2>;
+               };
        };
 };

diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd10ba720ccd52dd23c92d620ea2f6a9bc7ac3aa..d1690bc73bded1008c7bb8a3a3934abe54c4a471 100644 (file)
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/am33xx.h>
+#include <dt-bindings/clock/am3.h>
 
 / {
        compatible = "ti,am33xx";
@@ -578,7 +579,7 @@ rtc: rtc@44e3e000 {
                        interrupts = <75
                                      76>;
                        ti,hwmods = "rtc";
-                       clocks = <&clkdiv32k_ick>;
+                       clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
                        clock-names = "int-clk";
                };
 
@@ -1019,4 +1020,4 @@ rng: rng@48310000 {
        };
 };
 
-/include/ "am33xx-clocks.dtsi"
+#include "am33xx-clocks.dtsi"