ARM: dts: r8a7779: Add HSCIF0/1 device nodes

Based on Rev. 1.00 of the R-Car H1 datasheet.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 3bc133d9489c61374120d60752ec6755c4c75a71..3ff259207527555582da8e7c9393d5a981d456ee 100644 (file)
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -287,6 +287,32 @@ scif5: serial@ffe45000 {
                status = "disabled";
        };
 
+       hscif0: serial@ffe48000 {
+               compatible = "renesas,hscif-r8a7779",
+                            "renesas,rcar-gen1-hscif", "renesas,hscif";
+               reg = <0xffe48000 96>;
+               interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
+                        <&cpg_clocks R8A7779_CLK_S>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
+
+       hscif1: serial@ffe49000 {
+               compatible = "renesas,hscif-r8a7779",
+                            "renesas,rcar-gen1-hscif", "renesas,hscif";
+               reg = <0xffe49000 96>;
+               interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
+                        <&cpg_clocks R8A7779_CLK_S>,
+                        <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
+               power-domains = <&cpg_clocks>;
+               status = "disabled";
+       };
+
        pfc: pin-controller@fffc0000 {
                compatible = "renesas,pfc-r8a7779";
                reg = <0xfffc0000 0x23c>;