[IA64] Fix ISA IRQ trigger model and polarity setting

When handling Interrupt Source Override in MADT table, the default
ISA IRQ trigger model and polarity should be edge-rising.
Current IA64 implmentation doesn't follow the specification and
set default ISA IRQ trigger model as level-low. With that wrong
configuration and when system runs out of interrupt vectors,
it will cause vector sharing among edge triggered ISA IRQ and
level triggered PCI IRQ, then interrupt storm. So change the code
to follow the specification.

Signed-off-by: Liu Jiang <jiang.liu@huawei.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 5207035dc061bb5c567275efa0e0b58d2149a54d..2d801bfe16ac10b0aab83ade247c5474123d56f1 100644 (file)
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -349,11 +349,11 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
 
        iosapic_override_isa_irq(p->source_irq, p->global_irq,
                                 ((p->inti_flags & ACPI_MADT_POLARITY_MASK) ==
-                                 ACPI_MADT_POLARITY_ACTIVE_HIGH) ?
-                                IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
+                                 ACPI_MADT_POLARITY_ACTIVE_LOW) ?
+                                IOSAPIC_POL_LOW : IOSAPIC_POL_HIGH,
                                 ((p->inti_flags & ACPI_MADT_TRIGGER_MASK) ==
-                                ACPI_MADT_TRIGGER_EDGE) ?
-                                IOSAPIC_EDGE : IOSAPIC_LEVEL);
+                                ACPI_MADT_TRIGGER_LEVEL) ?
+                                IOSAPIC_LEVEL : IOSAPIC_EDGE);
        return 0;
 }