clk: socfpga: add divider registers to the main pll outputs

The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.

This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 501d513bf8905f02b60a1821877c7e280a3db2f0..dd3a78c64795f27c7e171f004f9bb0462f44579a 100644 (file)
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -32,7 +32,6 @@
 #define SOCFPGA_MMC_CLK                        "sdmmc_clk"
 #define SOCFPGA_GPIO_DB_CLK_OFFSET     0xA8
 
-#define div_mask(width)        ((1 << (width)) - 1)
 #define streq(a, b) (strcmp((a), (b)) == 0)
 
 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)

diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 81623a3736f912ba7a4847f52284df323e1c3b7e..46531c34ec9b5b58799c1c538c3f3ef103158502 100644 (file)
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -29,12 +29,18 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
                                             unsigned long parent_rate)
 {
        struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
-       u32 div;
+       u32 div, val;
 
-       if (socfpgaclk->fixed_div)
+       if (socfpgaclk->fixed_div) {
                div = socfpgaclk->fixed_div;
-       else
+       } else {
+               if (socfpgaclk->div_reg) {
+                       val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+                       val &= div_mask(socfpgaclk->width);
+                       parent_rate /= (val + 1);
+               }
                div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
+       }
 
        return parent_rate / div;
 }
@@ -54,6 +60,7 @@ static __init void __socfpga_periph_init(struct device_node *node,
        struct clk_init_data init;
        int rc;
        u32 fixed_div;
+       u32 div_reg[3];
 
        of_property_read_u32(node, "reg", &reg);
 
@@ -63,6 +70,15 @@ static __init void __socfpga_periph_init(struct device_node *node,
 
        periph_clk->hw.reg = clk_mgr_base_addr + reg;
 
+       rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+       if (!rc) {
+               periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+               periph_clk->shift = div_reg[1];
+               periph_clk->width = div_reg[2];
+       } else {
+               periph_clk->div_reg = 0;
+       }
+
        rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
        if (rc)
                periph_clk->fixed_div = 0;

diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index d2e54019c94fa32b3ef521036576691ddb14982f..d291f60c46e1adbbef48733388f1a1f0d40e31c5 100644 (file)
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -27,6 +27,7 @@
 #define CLKMGR_PERPLL_SRC      0xAC
 
 #define SOCFPGA_MAX_PARENTS            3
+#define div_mask(width) ((1 << (width)) - 1)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -52,6 +53,9 @@ struct socfpga_periph_clk {
        struct clk_gate hw;
        char *parent_name;
        u32 fixed_div;
+       void __iomem *div_reg;
+       u32 width;      /* only valid if div_reg != 0 */
+       u32 shift;      /* only valid if div_reg != 0 */
 };
 
 #endif /* SOCFPGA_CLK_H */