]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
cxgb4: collect hardware scheduler dumps
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Thu, 26 Oct 2017 11:48:39 +0000 (17:18 +0530)
committerDavid S. Miller <davem@davemloft.net>
Fri, 27 Oct 2017 14:48:30 +0000 (23:48 +0900)
Collect hardware TX traffic scheduler and pace tables.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

index 22853372abdffdb92bb0bdd44f8ac556273dc13f..9757609a86b9ff7d23a4ed906bc2480ea138623b 100644 (file)
@@ -49,6 +49,14 @@ struct cudbg_rss_vf_conf {
        u32 rss_vf_vfh;
 };
 
+struct cudbg_hw_sched {
+       u32 kbps[NTX_SCHED];
+       u32 ipg[NTX_SCHED];
+       u32 pace_tab[NTX_SCHED];
+       u32 mode;
+       u32 map;
+};
+
 struct ireg_field {
        u32 ireg_addr;
        u32 ireg_data;
index f672799cc8d3c71a9a80f6e363cd60af95cce2bc..e5c44b96d0a7b56bac9e9bc997f8786c5b27754b 100644 (file)
@@ -22,6 +22,7 @@
 #define CUDBG_STATUS_NO_MEM -19
 #define CUDBG_STATUS_ENTITY_NOT_FOUND -24
 #define CUDBG_SYSTEM_ERROR -29
+#define CUDBG_STATUS_CCLK_NOT_DEFINED -32
 
 #define CUDBG_MAJOR_VERSION 1
 #define CUDBG_MINOR_VERSION 14
@@ -48,6 +49,7 @@ enum cudbg_dbg_entity_type {
        CUDBG_EDC1 = 19,
        CUDBG_RSS = 22,
        CUDBG_RSS_VF_CONF = 25,
+       CUDBG_HW_SCHED = 31,
        CUDBG_TP_INDIRECT = 36,
        CUDBG_SGE_INDIRECT = 37,
        CUDBG_ULPRX_LA = 41,
index c4096967c434e5171a50a83c164f40a6d568bed1..0e01a2916ab8f82bc26724fe4fc232e29cf74346 100644 (file)
@@ -574,6 +574,31 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
        return rc;
 }
 
+int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
+                          struct cudbg_buffer *dbg_buff,
+                          struct cudbg_error *cudbg_err)
+{
+       struct adapter *padap = pdbg_init->adap;
+       struct cudbg_buffer temp_buff = { 0 };
+       struct cudbg_hw_sched *hw_sched_buff;
+       int i, rc = 0;
+
+       if (!padap->params.vpd.cclk)
+               return CUDBG_STATUS_CCLK_NOT_DEFINED;
+
+       rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_hw_sched),
+                           &temp_buff);
+       hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
+       hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
+       hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
+       t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
+       for (i = 0; i < NTX_SCHED; ++i)
+               t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
+                               &hw_sched_buff->ipg[i], true);
+       cudbg_write_and_release_buff(&temp_buff, dbg_buff);
+       return rc;
+}
+
 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
                              struct cudbg_buffer *dbg_buff,
                              struct cudbg_error *cudbg_err)
index 311b330bc3b271dd2988e26ab8c43ace0191473e..3f62c1900fe3fe93144d05246a83350214dc8684 100644 (file)
@@ -84,6 +84,9 @@ int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
 int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
                              struct cudbg_buffer *dbg_buff,
                              struct cudbg_error *cudbg_err);
+int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
+                          struct cudbg_buffer *dbg_buff,
+                          struct cudbg_error *cudbg_err);
 int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
                               struct cudbg_buffer *dbg_buff,
                               struct cudbg_error *cudbg_err);
index 92a0b022687ee7b139da3e8d69a48ab524cdcdd9..a57761b28edc65ea786c097b0a031e6746425ea2 100644 (file)
@@ -1335,6 +1335,12 @@ static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
                adapter->params.vpd.cclk);
 }
 
+static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
+                                             unsigned int ticks)
+{
+       return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
+}
+
 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
                      u32 val);
 
@@ -1636,6 +1642,9 @@ void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
                         int filter_index, int *enabled);
 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
                         u32 addr, u32 val);
+void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
+void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
+                    unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
                    int rateunit, int ratemode, int channel, int class,
                    int minrate, int maxrate, int weight, int pktsize);
index 003deb345ff2ff4178a9ba43581fa2425dcb24ce..35575e4d020c3769841cd8f20d0d90f7e5a91507 100644 (file)
@@ -46,6 +46,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
        { CUDBG_CIM_OBQ_NCSI, cudbg_collect_cim_obq_ncsi },
        { CUDBG_RSS, cudbg_collect_rss },
        { CUDBG_RSS_VF_CONF, cudbg_collect_rss_vf_config },
+       { CUDBG_HW_SCHED, cudbg_collect_hw_sched },
        { CUDBG_TP_INDIRECT, cudbg_collect_tp_indirect },
        { CUDBG_SGE_INDIRECT, cudbg_collect_sge_indirect },
        { CUDBG_ULPRX_LA, cudbg_collect_ulprx_la },
@@ -156,6 +157,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
                len = adap->params.arch.vfcount *
                      sizeof(struct cudbg_rss_vf_conf);
                break;
+       case CUDBG_HW_SCHED:
+               len = sizeof(struct cudbg_hw_sched);
+               break;
        case CUDBG_TP_INDIRECT:
                switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
                case CHELSIO_T5:
index 006414758f65915b5d4c962d8a1ba9515800637e..c289ca1efc1bc86546ad7e8f5db91548bdc9078a 100644 (file)
@@ -9547,6 +9547,63 @@ int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
        return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
 }
 
+/**
+ * t4_read_pace_tbl - read the pace table
+ * @adap: the adapter
+ * @pace_vals: holds the returned values
+ *
+ * Returns the values of TP's pace table in microseconds.
+ */
+void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
+{
+       unsigned int i, v;
+
+       for (i = 0; i < NTX_SCHED; i++) {
+               t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
+               v = t4_read_reg(adap, TP_PACE_TABLE_A);
+               pace_vals[i] = dack_ticks_to_usec(adap, v);
+       }
+}
+
+/**
+ * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
+ * @adap: the adapter
+ * @sched: the scheduler index
+ * @kbps: the byte rate in Kbps
+ * @ipg: the interpacket delay in tenths of nanoseconds
+ * @sleep_ok: if true we may sleep while awaiting command completion
+ *
+ * Return the current configuration of a HW Tx scheduler.
+ */
+void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
+                    unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
+{
+       unsigned int v, addr, bpt, cpt;
+
+       if (kbps) {
+               addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
+               t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
+               if (sched & 1)
+                       v >>= 16;
+               bpt = (v >> 8) & 0xff;
+               cpt = v & 0xff;
+               if (!cpt) {
+                       *kbps = 0;      /* scheduler disabled */
+               } else {
+                       v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
+                       *kbps = (v * bpt) / 125;
+               }
+       }
+       if (ipg) {
+               addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
+               t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
+               if (sched & 1)
+                       v >>= 16;
+               v &= 0xffff;
+               *ipg = (10000 * v) / core_ticks_per_usec(adap);
+       }
+}
+
 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
                    int rateunit, int ratemode, int channel, int class,
                    int minrate, int maxrate, int weight, int pktsize)
index 7f59ca458431d1c25c4f680a01c713e2858c730a..7c6af14905c2dd3257d29f67a2cf8b211cd3c7d0 100644 (file)
@@ -47,6 +47,7 @@ enum {
        TCB_SIZE       = 128,   /* TCB size */
        NMTUS          = 16,    /* size of MTU table */
        NCCTRL_WIN     = 32,    /* # of congestion control windows */
+       NTX_SCHED      = 8,     /* # of HW Tx scheduling queues */
        PM_NSTATS      = 5,     /* # of PM stats */
        T6_PM_NSTATS   = 7,     /* # of PM stats in T6 */
        MBOX_LEN       = 64,    /* mailbox size in bytes */
index 775a591c0fbac262bd0c4b1275092c72e0ce080f..483fb76443554e1ebc8f572ab1f8b8766602722d 100644 (file)
 #define ROWINDEX_V(x) ((x) << ROWINDEX_S)
 
 #define TP_CCTRL_TABLE_A       0x7ddc
+#define TP_PACE_TABLE_A 0x7dd8
 #define TP_MTU_TABLE_A         0x7de4
 
 #define MTUINDEX_S    24
 
 #define TP_TM_PIO_ADDR_A 0x7e18
 #define TP_TM_PIO_DATA_A 0x7e1c
+#define TP_MOD_CONFIG_A 0x7e24
+
+#define TIMERMODE_S    8
+#define TIMERMODE_M    0xffU
+#define TIMERMODE_G(x) (((x) >> TIMERMODE_S) & TIMERMODE_M)
+
+#define TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A 0x3
+#define TP_TX_MOD_Q1_Q0_RATE_LIMIT_A 0x8
+
 #define TP_PIO_ADDR_A  0x7e40
 #define TP_PIO_DATA_A  0x7e44
 #define TP_MIB_INDEX_A 0x7e50