]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amd/powerplay: add function display_configuration_changed for navi10
authorKevin Wang <kevin1.wang@amd.com>
Tue, 23 Apr 2019 06:16:52 +0000 (14:16 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 23:59:29 +0000 (18:59 -0500)
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
drivers/gpu/drm/amd/powerplay/vega20_ppt.c

index 50bdbb7c2908a13f1dc2210cdf1e2d50ce5ae5e4..bcd2adca6ed7bdf34ca6f32889c11061b224c1b8 100644 (file)
@@ -671,6 +671,30 @@ static int navi10_pre_display_config_changed(struct smu_context *smu)
        return ret;
 }
 
+static int navi10_display_config_changed(struct smu_context *smu)
+{
+       int ret = 0;
+
+       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+           !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+               ret = smu_write_watermarks_table(smu);
+               if (ret)
+                       return ret;
+
+               smu->watermarks_bitmap |= WATERMARKS_LOADED;
+       }
+
+       if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+           smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+           smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
+                                                 smu->display_config->num_display);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
 static const struct pptable_funcs navi10_ppt_funcs = {
        .tables_init = navi10_tables_init,
        .alloc_dpm_context = navi10_allocate_dpm_context,
@@ -691,6 +715,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .populate_umd_state_clk = navi10_populate_umd_state_clk,
        .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
        .pre_display_config_changed = navi10_pre_display_config_changed,
+       .display_config_changed = navi10_display_config_changed,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
index b0b8aeebe2ba768fc05962fd2cc85f406b0d00f8..ec7862ea299d093e26cb4c141e0e5b394582f9ee 100644 (file)
@@ -714,9 +714,21 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
 
 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 {
-       return smu_update_table(smu, SMU_TABLE_WATERMARKS,
-                               smu->smu_table.tables[SMU_TABLE_WATERMARKS].cpu_addr,
+       int ret = 0;
+       struct smu_table_context *smu_table = &smu->smu_table;
+       struct smu_table *table = NULL;
+
+       table = &smu_table->tables[SMU_TABLE_WATERMARKS];
+       if (!table)
+               return -EINVAL;
+
+       if (!table->cpu_addr)
+               return -EINVAL;
+
+       ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
                                true);
+
+       return ret;
 }
 
 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
index aea14f1a6395988227f3acc2e8b1a6c0cdae2b1b..63697fd3445f1acb05602b679354ae808254dcfc 100644 (file)
@@ -1992,17 +1992,9 @@ static int vega20_display_config_changed(struct smu_context *smu)
 {
        int ret = 0;
 
-       if (!smu->funcs)
-               return -EINVAL;
-
-       if (!smu->smu_dpm.dpm_context ||
-           !smu->smu_table.tables ||
-           !smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
-               return -EINVAL;
-
        if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
            !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
-               ret = smu->funcs->write_watermarks_table(smu);
+               ret = smu_write_watermarks_table(smu);
                if (ret) {
                        pr_err("Failed to update WMTABLE!");
                        return ret;