]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
net/mlx5: Enhance MCAM reg to allow query on access reg support
authorOr Gerlitz <ogerlitz@mellanox.com>
Sun, 11 Jun 2017 12:25:38 +0000 (15:25 +0300)
committerSaeed Mahameed <saeedm@mellanox.com>
Thu, 22 Jun 2017 11:30:13 +0000 (14:30 +0300)
Enhance MCAM to allow the driver to query which access regs are
supported. For now, expose the regs needed for FW flashing.

Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Reviewed-by: Gal Pressman <galp@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
include/linux/mlx5/device.h
include/linux/mlx5/mlx5_ifc.h

index b26a478930eb9010b662bd5ec1403f5b74170276..556e1c31b5d0852795b3b2873cd456263079cc96 100644 (file)
@@ -1094,6 +1094,9 @@ enum mlx5_mcam_feature_groups {
 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
        MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
 
+#define MLX5_CAP_MCAM_REG(mdev, reg) \
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
+
 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
        MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
 
index 28468ad804be9f1402d09cd44c6cbc68a9912683..8f197b070cea4c8f19f04f4e95221a3f736bf10d 100644 (file)
@@ -7745,6 +7745,18 @@ struct mlx5_ifc_mcam_enhanced_features_bits {
        u8         pcie_performance_group[0x1];
 };
 
+struct mlx5_ifc_mcam_access_reg_bits {
+       u8         reserved_at_0[0x1c];
+       u8         mcda[0x1];
+       u8         mcc[0x1];
+       u8         mcqi[0x1];
+       u8         reserved_at_1f[0x1];
+
+       u8         regs_95_to_64[0x20];
+       u8         regs_63_to_32[0x20];
+       u8         regs_31_to_0[0x20];
+};
+
 struct mlx5_ifc_mcam_reg_bits {
        u8         reserved_at_0[0x8];
        u8         feature_group[0x8];
@@ -7754,6 +7766,7 @@ struct mlx5_ifc_mcam_reg_bits {
        u8         reserved_at_20[0x20];
 
        union {
+               struct mlx5_ifc_mcam_access_reg_bits access_regs;
                u8         reserved_at_0[0x80];
        } mng_access_reg_cap_mask;