Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux...

Freescale updates from Scott:

"Includes a fix for a powerpc/next mm regression on 64e, a fix for a
kernel hang on 64e when using a debugger inside a relocated kernel, a
qman fix, and misc qe improvements."

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
index 349f79fd7076a63b3ad373e0d473f7e00f484c14..626e1afa64a6eb729f89e311ec67716167b45408 100644 (file)
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/gpio.txt
@@ -13,8 +13,17 @@ Required properties:
 - #gpio-cells : Should be two. The first cell is the pin number and the
   second cell is used to specify optional parameters (currently unused).
 - gpio-controller : Marks the port as GPIO controller.
+Optional properties:
+- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
+  on CPM1), this item tells which ports have an associated interrupt (ports are
+  listed in the same order as in PCINT register)
+- interrupts : This property provides the list of interrupt for each GPIO having
+  one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
+  many interrupts as number of ones in the mask property. The first interrupt in
+  the list corresponds to the most significant bit of the mask.
+- interrupt-parent : Parent for the above interrupt property.
 
-Example of three SOC GPIO banks defined as gpio-controller nodes:
+Example of four SOC GPIO banks defined as gpio-controller nodes:
 
        CPM1_PIO_A: gpio-controller@950 {
                #gpio-cells = <2>;
@@ -30,6 +39,16 @@ Example of three SOC GPIO banks defined as gpio-controller nodes:
                gpio-controller;
        };
 
+       CPM1_PIO_C: gpio-controller@960 {
+               #gpio-cells = <2>;
+               compatible = "fsl,cpm1-pario-bank-c";
+               reg = <0x960 0x10>;
+               fsl,cpm1-gpio-irq-mask = <0x0fff>;
+               interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
+               interrupt-parent = <&CPM_PIC>;
+               gpio-controller;
+       };
+
        CPM1_PIO_E: gpio-controller@ac8 {
                #gpio-cells = <2>;
                compatible = "fsl,cpm1-pario-bank-e";

diff --git a/arch/powerpc/include/asm/cpm1.h b/arch/powerpc/include/asm/cpm1.h
index 8ee4211ca0c6fb107cbf693c05fac5a987532822..14ad37865000f163c78ac727672bb0d85a45df40 100644 (file)
--- a/arch/powerpc/include/asm/cpm1.h
+++ b/arch/powerpc/include/asm/cpm1.h
@@ -560,6 +560,8 @@ typedef struct risc_timer_pram {
 #define CPM_PIN_SECONDARY 2
 #define CPM_PIN_GPIO      4
 #define CPM_PIN_OPENDRAIN 8
+#define CPM_PIN_FALLEDGE  16
+#define CPM_PIN_ANYEDGE   0
 
 enum cpm_port {
        CPM_PORTA,

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index a4b1d8d6b793319ea062e74a2bdcbd3b434405ab..a2123f291ab0c5c8dc13cc9364c3a12848a4bb2c 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -151,8 +151,13 @@ void release_thread(struct task_struct *);
 
 #ifdef __powerpc64__
 
+#ifdef CONFIG_PPC_BOOK3S_64
 /* Limit stack to 128TB */
 #define STACK_TOP_USER64 TASK_SIZE_128TB
+#else
+#define STACK_TOP_USER64 TASK_SIZE_USER64
+#endif
+
 #define STACK_TOP_USER32 TASK_SIZE_USER32
 
 #define STACK_TOP (is_32bit_task() ? \

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 45b453e4d0c87bf62c9100461bc33fb165f29931..acd8ca76233e871658bdb2b948d2652d273e0357 100644 (file)
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -735,8 +735,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
        andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
        beq+    1f
 
+#ifdef CONFIG_RELOCATABLE
+       ld      r15,PACATOC(r13)
+       ld      r14,interrupt_base_book3e@got(r15)
+       ld      r15,__end_interrupts@got(r15)
+#else
        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
        LOAD_REG_IMMEDIATE(r15,__end_interrupts)
+#endif
        cmpld   cr0,r10,r14
        cmpld   cr1,r10,r15
        blt+    cr0,1f
@@ -799,8 +805,14 @@ kernel_dbg_exc:
        andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
        beq+    1f
 
+#ifdef CONFIG_RELOCATABLE
+       ld      r15,PACATOC(r13)
+       ld      r14,interrupt_base_book3e@got(r15)
+       ld      r15,__end_interrupts@got(r15)
+#else
        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
        LOAD_REG_IMMEDIATE(r15,__end_interrupts)
+#endif
        cmpld   cr0,r10,r14
        cmpld   cr1,r10,r15
        blt+    cr0,1f

diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 986cd111d4df1064161238a6b2fabad474fa5260..c651e668996bc4d7c2592f8f9602c81147d1f3b6 100644 (file)
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -377,6 +377,10 @@ static void cpm1_set_pin16(int port, int pin, int flags)
                        setbits16(&iop->odr_sor, pin);
                else
                        clrbits16(&iop->odr_sor, pin);
+               if (flags & CPM_PIN_FALLEDGE)
+                       setbits16(&iop->intr, pin);
+               else
+                       clrbits16(&iop->intr, pin);
        }
 }
 
@@ -528,6 +532,9 @@ struct cpm1_gpio16_chip {
 
        /* shadowed data register to clear/set bits safely */
        u16 cpdata;
+
+       /* IRQ associated with Pins when relevant */
+       int irq[16];
 };
 
 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
@@ -578,6 +585,14 @@ static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
        spin_unlock_irqrestore(&cpm1_gc->lock, flags);
 }
 
+static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
+{
+       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+       struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
+
+       return cpm1_gc->irq[gpio] ? : -ENXIO;
+}
+
 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 {
        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
@@ -618,6 +633,7 @@ int cpm1_gpiochip_add16(struct device_node *np)
        struct cpm1_gpio16_chip *cpm1_gc;
        struct of_mm_gpio_chip *mm_gc;
        struct gpio_chip *gc;
+       u16 mask;
 
        cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
        if (!cpm1_gc)
@@ -625,6 +641,14 @@ int cpm1_gpiochip_add16(struct device_node *np)
 
        spin_lock_init(&cpm1_gc->lock);
 
+       if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
+               int i, j;
+
+               for (i = 0, j = 0; i < 16; i++)
+                       if (mask & (1 << (15 - i)))
+                               cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
+       }
+
        mm_gc = &cpm1_gc->mm_gc;
        gc = &mm_gc->gc;
 
@@ -634,6 +658,7 @@ int cpm1_gpiochip_add16(struct device_node *np)
        gc->direction_output = cpm1_gpio16_dir_out;
        gc->get = cpm1_gpio16_get;
        gc->set = cpm1_gpio16_set;
+       gc->to_irq = cpm1_gpio16_to_irq;
 
        return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
 }

diff --git a/drivers/net/ethernet/freescale/ucc_geth.c b/drivers/net/ethernet/freescale/ucc_geth.c
index 3f7ae9f64cd8771a834b104cec0b395c473a7bf2..f77ba9fa257b41a728ddd74176a465f4fadee2b8 100644 (file)
--- a/drivers/net/ethernet/freescale/ucc_geth.c
+++ b/drivers/net/ethernet/freescale/ucc_geth.c
@@ -2594,11 +2594,10 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
                } else if (ugeth->ug_info->uf_info.bd_mem_part ==
                           MEM_PART_MURAM) {
                        out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
-                                (u32) immrbar_virt_to_phys(ugeth->
-                                                           p_tx_bd_ring[i]));
+                                (u32)qe_muram_dma(ugeth->p_tx_bd_ring[i]));
                        out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
                                 last_bd_completed_address,
-                                (u32) immrbar_virt_to_phys(endOfRing));
+                                (u32)qe_muram_dma(endOfRing));
                }
        }
 
@@ -2844,8 +2843,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
                } else if (ugeth->ug_info->uf_info.bd_mem_part ==
                           MEM_PART_MURAM) {
                        out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
-                                (u32) immrbar_virt_to_phys(ugeth->
-                                                           p_rx_bd_ring[i]));
+                                (u32)qe_muram_dma(ugeth->p_rx_bd_ring[i]));
                }
                /* rest of fields handled by QE */
        }

diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 6f509f68085e9874a36bdecbc4587182e9e23d51..2827a65aa25a296add1d2a48bcc570b9bf99915a 100644 (file)
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -1344,6 +1344,7 @@ static void qm_congestion_task(struct work_struct *work)
        if (!qm_mc_result_timeout(&p->p, &mcr)) {
                spin_unlock(&p->cgr_lock);
                dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
+               qman_p_irqsource_add(p, QM_PIRQ_CSCI);
                return;
        }
        /* mask out the ones I'm not interested in */
@@ -1358,6 +1359,7 @@ static void qm_congestion_task(struct work_struct *work)
                if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
                        cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
        spin_unlock(&p->cgr_lock);
+       qman_p_irqsource_add(p, QM_PIRQ_CSCI);
 }
 
 static void qm_mr_process_task(struct work_struct *work)
@@ -1417,12 +1419,14 @@ static void qm_mr_process_task(struct work_struct *work)
        }
 
        qm_mr_cci_consume(&p->p, num);
+       qman_p_irqsource_add(p, QM_PIRQ_MRI);
        preempt_enable();
 }
 
 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
 {
        if (is & QM_PIRQ_CSCI) {
+               qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
                queue_work_on(smp_processor_id(), qm_portal_wq,
                              &p->congestion_work);
        }
@@ -1434,6 +1438,7 @@ static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
        }
 
        if (is & QM_PIRQ_MRI) {
+               qman_p_irqsource_remove(p, QM_PIRQ_MRI);
                queue_work_on(smp_processor_id(), qm_portal_wq,
                              &p->mr_work);
        }

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index ade168f5328e7fac1e68c4d55004cf94ac842f72..2ef6fc6487c113f8cb33aade2fa4f3d1d30f5454 100644 (file)
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -66,7 +66,7 @@ static unsigned int qe_num_of_snum;
 
 static phys_addr_t qebase = -1;
 
-phys_addr_t get_qe_base(void)
+static phys_addr_t get_qe_base(void)
 {
        struct device_node *qe;
        int ret;
@@ -90,8 +90,6 @@ phys_addr_t get_qe_base(void)
        return qebase;
 }
 
-EXPORT_SYMBOL(get_qe_base);
-
 void qe_reset(void)
 {
        if (qe_immr == NULL)
@@ -163,11 +161,15 @@ EXPORT_SYMBOL(qe_issue_cmd);
  */
 static unsigned int brg_clk = 0;
 
+#define CLK_GRAN       (1000)
+#define CLK_GRAN_LIMIT (5)
+
 unsigned int qe_get_brg_clk(void)
 {
        struct device_node *qe;
        int size;
        const u32 *prop;
+       unsigned int mod;
 
        if (brg_clk)
                return brg_clk;
@@ -185,10 +187,22 @@ unsigned int qe_get_brg_clk(void)
 
        of_node_put(qe);
 
+       /* round this if near to a multiple of CLK_GRAN */
+       mod = brg_clk % CLK_GRAN;
+       if (mod) {
+               if (mod < CLK_GRAN_LIMIT)
+                       brg_clk -= mod;
+               else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
+                       brg_clk += CLK_GRAN - mod;
+       }
+
        return brg_clk;
 }
 EXPORT_SYMBOL(qe_get_brg_clk);
 
+#define PVR_VER_836x   0x8083
+#define PVR_VER_832x   0x8084
+
 /* Program the BRG to the given sampling rate and multiplier
  *
  * @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -215,8 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
        /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
           that the BRG divisor must be even if you're not using divide-by-16
           mode. */
-       if (!div16 && (divisor & 1) && (divisor > 3))
-               divisor++;
+       if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+               if (!div16 && (divisor & 1) && (divisor > 3))
+                       divisor++;
 
        tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
                QE_BRGC_ENABLE | div16;

diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index a1048b44e6b93309499ddaac4bdb77d8b747c773..f744c214f680bf7343d7b8c8335573bcfc9bdd1b 100644 (file)
--- a/drivers/soc/fsl/qe/qe_tdm.c
+++ b/drivers/soc/fsl/qe/qe_tdm.c
@@ -177,6 +177,7 @@ int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
        devm_iounmap(&pdev->dev, utdm->si_regs);
        return ret;
 }
+EXPORT_SYMBOL(ucc_of_parse_tdm);
 
 void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
 {
@@ -274,3 +275,4 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
                break;
        }
 }
+EXPORT_SYMBOL(ucc_tdm_init);

diff --git a/include/soc/fsl/qe/immap_qe.h b/include/soc/fsl/qe/immap_qe.h
index c76ef30b05ba38ff517972125282c33ecc41b8eb..7baaabd5ec2ced0bf227691bdfea94ba9c53a0e4 100644 (file)
--- a/include/soc/fsl/qe/immap_qe.h
+++ b/include/soc/fsl/qe/immap_qe.h
@@ -464,25 +464,6 @@ struct qe_immap {
 } __attribute__ ((packed));
 
 extern struct qe_immap __iomem *qe_immr;
-extern phys_addr_t get_qe_base(void);
-
-/*
- * Returns the offset within the QE address space of the given pointer.
- *
- * Note that the QE does not support 36-bit physical addresses, so if
- * get_qe_base() returns a number above 4GB, the caller will probably fail.
- */
-static inline phys_addr_t immrbar_virt_to_phys(void *address)
-{
-       void *q = (void *)qe_immr;
-
-       /* Is it a MURAM address? */
-       if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
-               return get_qe_base() + (address - q);
-
-       /* It's an address returned by kmalloc */
-       return virt_to_phys(address);
-}
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_IMMAP_QE_H */

diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 70339d7958c02c2d8690509a5b62ef8a844bb7ff..0cd4c11479b1f4c4385c294295fdea4a7d82daa1 100644 (file)
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -243,6 +243,7 @@ static inline int qe_alive_during_sleep(void)
 #define qe_muram_free cpm_muram_free
 #define qe_muram_addr cpm_muram_addr
 #define qe_muram_offset cpm_muram_offset
+#define qe_muram_dma cpm_muram_dma
 
 #define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
 #define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))