ARM: dts: aspeed: Add aliases for UARTs

Existing userspace expects the console (UART5) to be at /dev/ttyS4.  To
ensure the UARTs show up where users expect them, we give them fixed
aliases starting at 0.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>

diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index e387c80b7f4f2257845939a8a0a49ec421e80349..be51be5a5f399f0fb5ee7ed810a2ae2956ae2de2 100644 (file)
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -6,10 +6,6 @@ / {
        model = "Palmetto BMC";
        compatible = "tyan,palmetto-bmc", "aspeed,ast2400";
 
-       aliases {
-               serial4 = &uart5;
-       };
-
        chosen {
                stdout-path = &uart5;
                bootargs = "console=ttyS4,115200 earlyprintk";

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b6ae7b62fd0379564d67092ff7b6f2fa1c8f8eda..a549413bda3f5e077235ad7e0ecf22199146631a 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -22,6 +22,11 @@ aliases {
                i2c11 = &i2c11;
                i2c12 = &i2c12;
                i2c13 = &i2c13;
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
        };
 
        cpus {

diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 4c829e915c3e6a796bf508232aa103fc92afbae3..de2dafa71651c5ece21fdc86b9a94c4ca51849be 100644 (file)
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -22,6 +22,11 @@ aliases {
                i2c11 = &i2c11;
                i2c12 = &i2c12;
                i2c13 = &i2c13;
+               serial0 = &uart1;
+               serial1 = &uart2;
+               serial2 = &uart3;
+               serial3 = &uart4;
+               serial4 = &uart5;
        };
 
        cpus {