ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q

This adds scu and general purpose registers device nodes required for
SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
address from general purpose (SW generic) register 1.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Jisheng Zhang <jszhang@marvell.com>
Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f10529bbfc473e0a8eff00bc1e1a9bf2c..4d85312dc17a1f6cfe7492d286192be76877e3a3 100644 (file)
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -72,6 +72,11 @@ l2: l2-cache-controller@ac0000 {
                        cache-level = <2>;
                };
 
+               scu: snoop-control-unit@ad0000 {
+                       compatible = "arm,cortex-a9-scu";
+                       reg = <0xad0000 0x58>;
+               };
+
                gic: interrupt-controller@ad1000 {
                        compatible = "arm,cortex-a9-gic";
                        reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@@ -176,6 +181,11 @@ aic: interrupt-controller@3000 {
                        };
                };
 
+               generic-regs@ea0184 {
+                       compatible = "marvell,berlin-generic-regs", "syscon";
+                       reg = <0xea0184 0x10>;
+               };
+
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 07452a7483fade2975ead25b18b0a6845ffe474a..86d8a2c49f38d6ae295075257da398828771b4a1 100644 (file)
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -87,6 +87,11 @@ l2: l2-cache-controller@ac0000 {
                        cache-level = <2>;
                };
 
+               scu: snoop-control-unit@ad0000 {
+                       compatible = "arm,cortex-a9-scu";
+                       reg = <0xad0000 0x58>;
+               };
+
                local-timer@ad0600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
@@ -183,6 +188,11 @@ aic: interrupt-controller@3800 {
                        };
                };
 
+               generic-regs@ea0110 {
+                       compatible = "marvell,berlin-generic-regs", "syscon";
+                       reg = <0xea0110 0x10>;
+               };
+
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;