clk: sunxi-ng: h3: Fix audio clock divider offset

The code had a typo and got the wrong offset for the hardcoded divider, fix
that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index bcc0a95549d3f1bcdd6e711fab86d2ae71a48a67..9af359544110b59fd61dca76e69a7b922107fb15 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
 
        /* Force the PLL-Audio-1x divider to 4 */
        val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
-       val &= ~GENMASK(4, 0);
-       writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
+       val &= ~GENMASK(19, 16);
+       writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
 
        sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
 }