MIPS: uasm: Add div, mul and sel instructions for mipsr6

Add the following instructions for use by eBPF on mipsr6:
insn_ddivu_r6, insn_divu_r6, insn_dmodu, insn_dmulu, insn_modu,
insn_mulu, insn_seleqz, insn_selnez

Signed-off-by: Hassan Naveed <hnaveed@wavecomp.com>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: kafai@fb.com
Cc: songliubraving@fb.com
Cc: yhs@fb.com
Cc: netdev@vger.kernel.org
Cc: bpf@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Cc: open list:MIPS <linux-mips@linux-mips.org>
Cc: open list <linux-kernel@vger.kernel.org>

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index b1990dd75f274927e6acbf7f5f05b49f5de596d5..f7effca791a50f2abf021fa63740d0208f1ddde2 100644 (file)
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -86,14 +86,18 @@ Ip_u2u1(_ctcmsa);
 Ip_u2u1s3(_daddiu);
 Ip_u3u1u2(_daddu);
 Ip_u1u2(_ddivu);
+Ip_u3u1u2(_ddivu_r6);
 Ip_u1(_di);
 Ip_u2u1msbu3(_dins);
 Ip_u2u1msbu3(_dinsm);
 Ip_u2u1msbu3(_dinsu);
 Ip_u1u2(_divu);
+Ip_u3u1u2(_divu_r6);
 Ip_u1u2u3(_dmfc0);
+Ip_u3u1u2(_dmodu);
 Ip_u1u2u3(_dmtc0);
 Ip_u1u2(_dmultu);
+Ip_u3u1u2(_dmulu);
 Ip_u2u1u3(_drotr);
 Ip_u2u1u3(_drotr32);
 Ip_u2u1(_dsbh);
@@ -131,6 +135,7 @@ Ip_u1u2u3(_mfc0);
 Ip_u1u2u3(_mfhc0);
 Ip_u1(_mfhi);
 Ip_u1(_mflo);
+Ip_u3u1u2(_modu);
 Ip_u3u1u2(_movn);
 Ip_u3u1u2(_movz);
 Ip_u1u2u3(_mtc0);
@@ -139,6 +144,7 @@ Ip_u1(_mthi);
 Ip_u1(_mtlo);
 Ip_u3u1u2(_mul);
 Ip_u1u2(_multu);
+Ip_u3u1u2(_mulu);
 Ip_u3u1u2(_nor);
 Ip_u3u1u2(_or);
 Ip_u2u1u3(_ori);
@@ -149,6 +155,8 @@ Ip_u2s3u1(_sb);
 Ip_u2s3u1(_sc);
 Ip_u2s3u1(_scd);
 Ip_u2s3u1(_sd);
+Ip_u3u1u2(_seleqz);
+Ip_u3u1u2(_selnez);
 Ip_u2s3u1(_sh);
 Ip_u2u1u3(_sll);
 Ip_u3u2u1(_sllv);

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 40fbb5dd66dfb06dbc9777b24731bc6727265074..eaa3a80affdf756e7921ad73ba66c961823cc83f 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -55,9 +55,9 @@ enum spec_op {
        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
        dadd_op, daddu_op, dsub_op, dsubu_op,
        tge_op, tgeu_op, tlt_op, tltu_op,
-       teq_op, spec5_unused_op, tne_op, spec6_unused_op,
-       dsll_op, spec7_unused_op, dsrl_op, dsra_op,
-       dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
+       teq_op, seleqz_op, tne_op, selnez_op,
+       dsll_op, spec5_unused_op, dsrl_op, dsra_op,
+       dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op
 };
 
 /*

diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 6abe40fc413ddccfe2e7af60ea307b1fc42f08e1..7154a1d99aad6131dd1e33811f4bc863c2ab30d5 100644 (file)
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -76,14 +76,22 @@ static const struct insn insn_table[insn_invalid] = {
        [insn_daddiu]   = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
        [insn_daddu]    = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
        [insn_ddivu]    = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
+       [insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
+                               RS | RT | RD},
        [insn_di]       = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
        [insn_dins]     = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
        [insn_dinsm]    = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
        [insn_dinsu]    = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
        [insn_divu]     = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
+       [insn_divu_r6]  = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
+                               RS | RT | RD},
        [insn_dmfc0]    = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
+       [insn_dmodu]    = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
+                               RS | RT | RD},
        [insn_dmtc0]    = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
        [insn_dmultu]   = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
+       [insn_dmulu]    = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
+                               RS | RT | RD},
        [insn_drotr]    = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
        [insn_drotr32]  = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
        [insn_dsbh]     = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
@@ -132,12 +140,16 @@ static const struct insn insn_table[insn_invalid] = {
        [insn_mfhc0]    = {M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
        [insn_mfhi]     = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
        [insn_mflo]     = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
+       [insn_modu]     = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
+                               RS | RT | RD},
        [insn_movn]     = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
        [insn_movz]     = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
        [insn_mtc0]     = {M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
        [insn_mthc0]    = {M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
        [insn_mthi]     = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
        [insn_mtlo]     = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
+       [insn_mulu]     = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
+                               RS | RT | RD},
 #ifndef CONFIG_CPU_MIPSR6
        [insn_mul]      = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
 #else
@@ -163,6 +175,8 @@ static const struct insn insn_table[insn_invalid] = {
        [insn_scd]      = {M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9},
 #endif
        [insn_sd]       = {M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
+       [insn_seleqz]   = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
+       [insn_selnez]   = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
        [insn_sh]       = {M(sh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
        [insn_sll]      = {M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE},
        [insn_sllv]     = {M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD},

diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 45b6264ff308f713ce555cfcf16e603bb59a795b..c56f129c9a4ba400e70a3be459b689f4fd103b25 100644 (file)
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -50,21 +50,22 @@ enum opcode {
        insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
        insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
        insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
-       insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
-       insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
-       insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
-       insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
-       insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
-       insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
-       insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
-       insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
-       insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
-       insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
-       insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
-       insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav,
-       insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
-       insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
-       insn_xor, insn_xori, insn_yield,
+       insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
+       insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
+       insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
+       insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
+       insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
+       insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
+       insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
+       insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
+       insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
+       insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
+       insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
+       insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
+       insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
+       insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
+       insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
+       insn_wsbh, insn_xor, insn_xori, insn_yield,
        insn_invalid /* insn_invalid must be last */
 };
 
@@ -287,13 +288,17 @@ I_u2u1(_cfcmsa)
 I_u1u2(_ctc1)
 I_u2u1(_ctcmsa)
 I_u1u2(_ddivu)
+I_u3u1u2(_ddivu_r6)
 I_u1u2u3(_dmfc0)
+I_u3u1u2(_dmodu)
 I_u1u2u3(_dmtc0)
 I_u1u2(_dmultu)
+I_u3u1u2(_dmulu)
 I_u2u1s3(_daddiu)
 I_u3u1u2(_daddu)
 I_u1(_di);
 I_u1u2(_divu)
+I_u3u1u2(_divu_r6)
 I_u2u1(_dsbh);
 I_u2u1(_dshd);
 I_u2u1u3(_dsll)
@@ -327,6 +332,7 @@ I_u2s3u1(_lw)
 I_u2s3u1(_lwu)
 I_u1u2u3(_mfc0)
 I_u1u2u3(_mfhc0)
+I_u3u1u2(_modu)
 I_u3u1u2(_movn)
 I_u3u1u2(_movz)
 I_u1(_mfhi)
@@ -337,6 +343,7 @@ I_u1(_mthi)
 I_u1(_mtlo)
 I_u3u1u2(_mul)
 I_u1u2(_multu)
+I_u3u1u2(_mulu)
 I_u3u1u2(_nor)
 I_u3u1u2(_or)
 I_u2u1u3(_ori)
@@ -345,6 +352,8 @@ I_u2s3u1(_sb)
 I_u2s3u1(_sc)
 I_u2s3u1(_scd)
 I_u2s3u1(_sd)
+I_u3u1u2(_seleqz)
+I_u3u1u2(_selnez)
 I_u2s3u1(_sh)
 I_u2u1u3(_sll)
 I_u3u2u1(_sllv)