arm64: dts: exynos: Swap clock order of sysmmu on Exynos5433

dt-schema supports only order of names "aclk", "pclk".  Swap some sysmmu
definitions to make them compatible with schema.

Signed-off-by: Maciej Falkowski <m.falkowski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index f6953073021980052c47fcc3cee8abeead942497..446bcd26812ceac8579393289d9b909cacfdca7b 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1179,9 +1179,9 @@ sysmmu_decon0x: sysmmu@13a00000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a00000 0x1000>;
                        interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
-                               <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
+                               <&cmu_disp CLK_PCLK_SMMU_DECON0X>;
                        power-domains = <&pd_disp>;
                        #iommu-cells = <0>;
                };
@@ -1190,9 +1190,9 @@ sysmmu_decon1x: sysmmu@13a10000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a10000 0x1000>;
                        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
-                               <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+                               <&cmu_disp CLK_PCLK_SMMU_DECON1X>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_disp>;
                };
@@ -1201,9 +1201,9 @@ sysmmu_tv0x: sysmmu@13a20000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a20000 0x1000>;
                        interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
-                               <&cmu_disp CLK_ACLK_SMMU_TV0X>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
+                               <&cmu_disp CLK_PCLK_SMMU_TV0X>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_disp>;
                };
@@ -1212,9 +1212,9 @@ sysmmu_tv1x: sysmmu@13a30000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a30000 0x1000>;
                        interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
-                               <&cmu_disp CLK_ACLK_SMMU_TV1X>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
+                               <&cmu_disp CLK_PCLK_SMMU_TV1X>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_disp>;
                };
@@ -1256,9 +1256,9 @@ sysmmu_scaler_0: sysmmu@15040000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15040000 0x1000>;
                        interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>,
-                                <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
+                               <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_mscl>;
                };
@@ -1267,9 +1267,9 @@ sysmmu_scaler_1: sysmmu@15050000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15050000 0x1000>;
                        interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>,
-                                <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
+                               <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_mscl>;
                };
@@ -1278,9 +1278,9 @@ sysmmu_jpeg: sysmmu@15060000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15060000 0x1000>;
                        interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
-                                <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
+                               <&cmu_mscl CLK_PCLK_SMMU_JPEG>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_mscl>;
                };
@@ -1289,9 +1289,9 @@ sysmmu_mfc_0: sysmmu@15200000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15200000 0x1000>;
                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
-                                <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
+                               <&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_mfc>;
                };
@@ -1300,9 +1300,9 @@ sysmmu_mfc_1: sysmmu@15210000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x15210000 0x1000>;
                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                       clock-names = "pclk", "aclk";
-                       clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
-                                <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
+                       clock-names = "aclk", "pclk";
+                       clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
+                               <&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
                        #iommu-cells = <0>;
                        power-domains = <&pd_mfc>;
                };