]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: r8a7743: Add DU support
authorFabrizio Castro <fabrizio.castro@bp.renesas.com>
Mon, 23 Oct 2017 18:09:21 +0000 (19:09 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 27 Nov 2017 10:39:44 +0000 (11:39 +0100)
Add du node to r8a7743 SoC DT. Boards that want to enable the DU
need to specify the output topology.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7743.dtsi

index f647b86c0205fb4e726c7cb4d8780e0ac234c0ff..112a72baa7a4f660c248c0455b08516ed1d0640d 100644 (file)
@@ -1034,6 +1034,36 @@ usb2: usb-channel@2 {
                        };
                };
 
+               du: display@feb00000 {
+                       compatible = "renesas,du-r8a7743";
+                       reg = <0 0xfeb00000 0 0x40000>,
+                             <0 0xfeb90000 0 0x1c>;
+                       reg-names = "du", "lvds.0";
+                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 724>,
+                                <&cpg CPG_MOD 723>,
+                                <&cpg CPG_MOD 726>;
+                       clock-names = "du.0", "du.1", "lvds.0";
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_rgb: endpoint {
+                                       };
+                               };
+                               port@1 {
+                                       reg = <1>;
+                                       du_out_lvds0: endpoint {
+                                       };
+                               };
+                       };
+               };
+
                pci0: pci@ee090000 {
                        compatible = "renesas,pci-r8a7743",
                                     "renesas,pci-rcar-gen2";