arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver

The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
connections. It is very similar to the device found in the Allwinner
H3, but lacks the internal 100 Mbit PHY and its associated control
bits.
This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
it disabled at this level.

Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d7341baa6b7e3db45bdc38150f3d587ab4be14e1..18b3642e51cb588c1f6338844c7ea18a6516a4bd 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -287,6 +287,21 @@ mmc2_pins: mmc2-pins {
                                bias-pull-up;
                        };
 
+                       rmii_pins: rmii_pins {
+                               pins = "PD10", "PD11", "PD13", "PD14", "PD17",
+                                      "PD18", "PD19", "PD20", "PD22", "PD23";
+                               function = "emac";
+                               drive-strength = <40>;
+                       };
+
+                       rgmii_pins: rgmii_pins {
+                               pins = "PD8", "PD9", "PD10", "PD11", "PD12",
+                                      "PD13", "PD15", "PD16", "PD17", "PD18",
+                                      "PD19", "PD20", "PD21", "PD22", "PD23";
+                               function = "emac";
+                               drive-strength = <40>;
+                       };
+
                        uart0_pins_a: uart0@0 {
                                pins = "PB8", "PB9";
                                function = "uart0";
@@ -391,6 +406,26 @@ i2c2: i2c@1c2b400 {
                        #size-cells = <0>;
                };
 
+               emac: ethernet@1c30000 {
+                       compatible = "allwinner,sun50i-a64-emac";
+                       syscon = <&syscon>;
+                       reg = <0x01c30000 0x100>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq";
+                       resets = <&ccu RST_BUS_EMAC>;
+                       reset-names = "stmmaceth";
+                       clocks = <&ccu CLK_BUS_EMAC>;
+                       clock-names = "stmmaceth";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       mdio: mdio {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                       };
+               };
+
                gic: interrupt-controller@1c81000 {
                        compatible = "arm,gic-400";
                        reg = <0x01c81000 0x1000>,