serial: tegra: Add delay after enabling FIFO mode

For all tegra devices (up to t210), there is a hardware issue that
requires software to wait for 3 UART clock periods after enabling
the TX fifo, otherwise data could be lost.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 9e08d3f07509310ad2e340f702599eee780356af..0d9d7ceb1dbbbfb872bd8e5c27d92d5d8a95c8a6 100644 (file)
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -885,6 +885,16 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
        tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
        tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
 
+       /* Dummy read to ensure the write is posted */
+       tegra_uart_read(tup, UART_SCR);
+
+       /*
+        * For all tegra devices (up to t210), there is a hardware issue that
+        * requires software to wait for 3 UART clock periods after enabling
+        * the TX fifo, otherwise data could be lost.
+        */
+       tegra_uart_wait_cycle_time(tup, 3);
+
        /*
         * Initialize the UART with default configuration
         * (115200, N, 8, 1) so that the receive DMA buffer may be