]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Wed, 28 Jun 2017 20:14:01 +0000 (15:14 -0500)
committerBjorn Helgaas <bhelgaas@google.com>
Sun, 2 Jul 2017 21:14:27 +0000 (16:14 -0500)
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to
scan a PCI root bus backed by an already initialized struct pci_host_bridge
object, which simplifies the bus scan interface and makes the PCI scan root
bus interface easier to generalize as members are added to the struct
pci_host_bridge.

Convert PCI xilinx-nwl host code to pci_scan_root_bus_bridge() to improve
the PCI root bus scanning interface.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
drivers/pci/host/pcie-xilinx-nwl.c

index 26e66e8eebbb671e5d7e59ffd5fe2e7fbd678bd4..e8a589431008ccc4a3cfed86fedecf96f5e65c6b 100644 (file)
@@ -791,13 +791,16 @@ static int nwl_pcie_probe(struct platform_device *pdev)
        struct nwl_pcie *pcie;
        struct pci_bus *bus;
        struct pci_bus *child;
+       struct pci_host_bridge *bridge;
        int err;
        resource_size_t iobase = 0;
        LIST_HEAD(res);
 
-       pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
-       if (!pcie)
-               return -ENOMEM;
+       bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
+       if (!bridge)
+               return -ENODEV;
+
+       pcie = pci_host_bridge_priv(bridge);
 
        pcie->dev = dev;
        pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
@@ -830,12 +833,11 @@ static int nwl_pcie_probe(struct platform_device *pdev)
                goto error;
        }
 
-       bus = pci_create_root_bus(dev, pcie->root_busno,
-                                 &nwl_pcie_ops, pcie, &res);
-       if (!bus) {
-               err = -ENOMEM;
-               goto error;
-       }
+       list_splice_init(&res, &bridge->windows);
+       bridge->dev.parent = dev;
+       bridge->sysdata = pcie;
+       bridge->busnr = pcie->root_busno;
+       bridge->ops = &nwl_pcie_ops;
 
        if (IS_ENABLED(CONFIG_PCI_MSI)) {
                err = nwl_pcie_enable_msi(pcie);
@@ -844,7 +846,13 @@ static int nwl_pcie_probe(struct platform_device *pdev)
                        goto error;
                }
        }
-       pci_scan_child_bus(bus);
+
+       err = pci_scan_root_bus_bridge(bridge);
+       if (err)
+               goto error;
+
+       bus = bridge->bus;
+
        pci_assign_unassigned_bus_resources(bus);
        list_for_each_entry(child, &bus->children, node)
                pcie_bus_configure_settings(child);