drm/i915/selftests: Check a few more fixed locations within the context image

As we use hard coded offsets for a few locations within the context
image, include those in the selftests to assert that they are valid.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191028121803.29408-1-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index ba7fc4397bd984ead8d4bd1c24f4bf59311e1816..9507d750ae14df14eab291a10ca046095256b081 100644 (file)
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -3194,10 +3194,35 @@ static int live_lrc_fixed(void *arg)
                        u32 offset;
                        const char *name;
                } tbl[] = {
+                       {
+                               i915_mmio_reg_offset(RING_START(engine->mmio_base)),
+                               CTX_RING_BUFFER_START - 1,
+                               "RING_START"
+                       },
+                       {
+                               i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),
+                               CTX_RING_BUFFER_CONTROL - 1,
+                               "RING_CTL"
+                       },
+                       {
+                               i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),
+                               CTX_RING_HEAD - 1,
+                               "RING_HEAD"
+                       },
+                       {
+                               i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),
+                               CTX_RING_TAIL - 1,
+                               "RING_TAIL"
+                       },
                        {
                                i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
                                lrc_ring_mi_mode(engine),
-                               "RING_MI_MODE",
+                               "RING_MI_MODE"
+                       },
+                       {
+                               engine->mmio_base + 0x110,
+                               CTX_BB_STATE - 1,
+                               "BB_STATE"
                        },
                        { },
                }, *t;