drm/amdgpu: add psp funcs for ring write pointer read/write

The ring write pointer regsiter update is the only part that
is IP specific ones in psp_cmd_submit function.

Add two callbacks for wptr read/write so that we unify the
psp_cmd_submit function for all the ASICs.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 09c5474ebcc348b7b4461395832c9511092aed31..d5620c46f3fc72e42ec4be4809ef95dfcf238470 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -116,6 +116,8 @@ struct psp_funcs
        int (*mem_training_init)(struct psp_context *psp);
        void (*mem_training_fini)(struct psp_context *psp);
        int (*mem_training)(struct psp_context *psp, uint32_t ops);
+       uint32_t (*ring_get_wptr)(struct psp_context *psp);
+       void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
 };
 
 #define AMDGPU_XGMI_MAX_CONNECTED_NODES                64
@@ -346,6 +348,9 @@ struct amdgpu_psp_funcs {
        ((psp)->funcs->ras_cure_posion ? \
        (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
 
+#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
+#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
+
 extern const struct amd_ip_funcs psp_ip_funcs;
 
 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index b345e69ba2460d5850aadd67701909adcadfe731..4b8fdddc4c4667139e2a8b0085e18fde31125c78 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -407,6 +407,20 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp)
        return -EINVAL;
 }
 
+static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+}
+
+static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
+}
+
 static const struct psp_funcs psp_v10_0_funcs = {
        .init_microcode = psp_v10_0_init_microcode,
        .ring_init = psp_v10_0_ring_init,
@@ -416,6 +430,8 @@ static const struct psp_funcs psp_v10_0_funcs = {
        .cmd_submit = psp_v10_0_cmd_submit,
        .compare_sram_data = psp_v10_0_compare_sram_data,
        .mode1_reset = psp_v10_0_mode1_reset,
+       .ring_get_wptr = psp_v10_0_ring_get_wptr,
+       .ring_set_wptr = psp_v10_0_ring_set_wptr,
 };
 
 void psp_v10_0_set_psp_funcs(struct psp_context *psp)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index ffeaa2f5588d05757fce353eaa5550a9a1253970..5cd2733aa2eaa452aa3ce248ffe7b735227237c2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -1068,6 +1068,30 @@ static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
        return 0;
 }
 
+static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
+{
+       uint32_t data;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v11_0_support_vmr_ring(psp))
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+       else
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+
+       return data;
+}
+
+static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v11_0_support_vmr_ring(psp)) {
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+       } else
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
+}
+
 static const struct psp_funcs psp_v11_0_funcs = {
        .init_microcode = psp_v11_0_init_microcode,
        .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
@@ -1091,6 +1115,8 @@ static const struct psp_funcs psp_v11_0_funcs = {
        .mem_training_init = psp_v11_0_memory_training_init,
        .mem_training_fini = psp_v11_0_memory_training_fini,
        .mem_training = psp_v11_0_memory_training,
+       .ring_get_wptr = psp_v11_0_ring_get_wptr,
+       .ring_set_wptr = psp_v11_0_ring_set_wptr,
 };
 
 void psp_v11_0_set_psp_funcs(struct psp_context *psp)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index 8f553f6f92d61b1a117b485e4a667fd0415d5f48..75b3f9d15a18733390071588f131e9f263bcc325 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -547,6 +547,30 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
        return 0;
 }
 
+static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
+{
+       uint32_t data;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v12_0_support_vmr_ring(psp))
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+       else
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+
+       return data;
+}
+
+static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v12_0_support_vmr_ring(psp)) {
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+       } else
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
+}
+
 static const struct psp_funcs psp_v12_0_funcs = {
        .init_microcode = psp_v12_0_init_microcode,
        .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
@@ -558,6 +582,8 @@ static const struct psp_funcs psp_v12_0_funcs = {
        .cmd_submit = psp_v12_0_cmd_submit,
        .compare_sram_data = psp_v12_0_compare_sram_data,
        .mode1_reset = psp_v12_0_mode1_reset,
+       .ring_get_wptr = psp_v12_0_ring_get_wptr,
+       .ring_set_wptr = psp_v12_0_ring_set_wptr,
 };
 
 void psp_v12_0_set_psp_funcs(struct psp_context *psp)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index fdc00938327b8b60e73c9e93429862f76dd64cb9..bee6514f04a9b6694f706be6f3e6d2217552ca24 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -642,6 +642,31 @@ static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
        return false;
 }
 
+static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
+{
+       uint32_t data;
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v3_1_support_vmr_ring(psp))
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+       else
+               data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+       return data;
+}
+
+static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       if (psp_v3_1_support_vmr_ring(psp)) {
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
+               /* send interrupt to PSP for SRIOV ring write pointer update */
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+                       GFX_CTRL_CMD_ID_CONSUME_CMD);
+       } else
+               WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
+}
+
 static const struct psp_funcs psp_v3_1_funcs = {
        .init_microcode = psp_v3_1_init_microcode,
        .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
@@ -655,6 +680,8 @@ static const struct psp_funcs psp_v3_1_funcs = {
        .smu_reload_quirk = psp_v3_1_smu_reload_quirk,
        .mode1_reset = psp_v3_1_mode1_reset,
        .support_vmr_ring = psp_v3_1_support_vmr_ring,
+       .ring_get_wptr = psp_v3_1_ring_get_wptr,
+       .ring_set_wptr = psp_v3_1_ring_set_wptr,
 };
 
 void psp_v3_1_set_psp_funcs(struct psp_context *psp)