igc: Remove the obsolete workaround

Enables a resend request after the completion timeout workaround is not
relevant for i225 device. This patch is clean code relevant this
workaround.
Minor cosmetic fixes, replace the 'spaces' with 'tabs'

Signed-off-by: Sasha Neftin <sasha.neftin@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/igc/igc_base.c b/drivers/net/ethernet/intel/igc/igc_base.c
index 51a8b8769c67eab2031285639063e896577b0724..59258d7911060267f88c9cd0a618e606114ba556 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_base.c
+++ b/drivers/net/ethernet/intel/igc/igc_base.c
@@ -9,50 +9,6 @@
 #include "igc_base.h"
 #include "igc.h"
 
-/**
- * igc_set_pcie_completion_timeout - set pci-e completion timeout
- * @hw: pointer to the HW structure
- */
-static s32 igc_set_pcie_completion_timeout(struct igc_hw *hw)
-{
-       u32 gcr = rd32(IGC_GCR);
-       u16 pcie_devctl2;
-       s32 ret_val = 0;
-
-       /* only take action if timeout value is defaulted to 0 */
-       if (gcr & IGC_GCR_CMPL_TMOUT_MASK)
-               goto out;
-
-       /* if capabilities version is type 1 we can write the
-        * timeout of 10ms to 200ms through the GCR register
-        */
-       if (!(gcr & IGC_GCR_CAP_VER2)) {
-               gcr |= IGC_GCR_CMPL_TMOUT_10ms;
-               goto out;
-       }
-
-       /* for version 2 capabilities we need to write the config space
-        * directly in order to set the completion timeout value for
-        * 16ms to 55ms
-        */
-       ret_val = igc_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-                                       &pcie_devctl2);
-       if (ret_val)
-               goto out;
-
-       pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
-
-       ret_val = igc_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-                                        &pcie_devctl2);
-out:
-       /* disable completion timeout resend */
-       gcr &= ~IGC_GCR_CMPL_TMOUT_RESEND;
-
-       wr32(IGC_GCR, gcr);
-
-       return ret_val;
-}
-
 /**
  * igc_reset_hw_base - Reset hardware
  * @hw: pointer to the HW structure
@@ -72,11 +28,6 @@ static s32 igc_reset_hw_base(struct igc_hw *hw)
        if (ret_val)
                hw_dbg("PCI-E Master disable polling has failed.\n");
 
-       /* set the completion timeout for interface */
-       ret_val = igc_set_pcie_completion_timeout(hw);
-       if (ret_val)
-               hw_dbg("PCI-E Set completion timeout has failed.\n");
-
        hw_dbg("Masking off all interrupts\n");
        wr32(IGC_IMC, 0xffffffff);
 

diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h
index 6f17ed3de9955b075b7ec0676c3d98f14a821e7f..5f6bc67cb33bafbc75c879184691392c5fac1aaf 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_defines.h
+++ b/drivers/net/ethernet/intel/igc/igc_defines.h
@@ -5,8 +5,8 @@
 #define _IGC_DEFINES_H_
 
 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define REQ_TX_DESCRIPTOR_MULTIPLE  8
-#define REQ_RX_DESCRIPTOR_MULTIPLE  8
+#define REQ_TX_DESCRIPTOR_MULTIPLE     8
+#define REQ_RX_DESCRIPTOR_MULTIPLE     8
 
 #define IGC_CTRL_EXT_DRV_LOAD  0x10000000 /* Drv loaded bit for FW */
 
@@ -29,12 +29,6 @@
 /* Status of Master requests. */
 #define IGC_STATUS_GIO_MASTER_ENABLE   0x00080000
 
-/* PCI Express Control */
-#define IGC_GCR_CMPL_TMOUT_MASK                0x0000F000
-#define IGC_GCR_CMPL_TMOUT_10ms                0x00001000
-#define IGC_GCR_CMPL_TMOUT_RESEND      0x00010000
-#define IGC_GCR_CAP_VER2               0x00040000
-
 /* Receive Address
  * Number of high/low register pairs in the RAR. The RAR (Receive Address
  * Registers) holds the directed and multicast addresses that we monitor.
@@ -395,7 +389,7 @@
 #define IGC_MDIC_ERROR         0x40000000
 #define IGC_MDIC_DEST          0x80000000
 
-#define IGC_N0_QUEUE -1
+#define IGC_N0_QUEUE           -1
 
 #define IGC_MAX_MAC_HDR_LEN    127
 #define IGC_MAX_NETWORK_HDR_LEN        511