]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: sun6i: Add default address and size cells for SPI
authorMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 20 May 2019 14:50:36 +0000 (16:50 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Tue, 21 May 2019 14:29:15 +0000 (16:29 +0200)
The SPI controller bindings require an address cell size of 1, and a size
cell size of 0. Let's put it at the DTSI level to make sure that's properly
enforced.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
arch/arm/boot/dts/sun6i-a31.dtsi

index c04efad81bbc9eb05135e6b84b7c786684b7ebf8..a57cbf33c12f24b8d3ed2fe0f7bb20fa83ba6a18 100644 (file)
@@ -987,6 +987,8 @@ spi0: spi@1c68000 {
                        dma-names = "rx", "tx";
                        resets = <&ccu RST_AHB1_SPI0>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                spi1: spi@1c69000 {
@@ -999,6 +1001,8 @@ spi1: spi@1c69000 {
                        dma-names = "rx", "tx";
                        resets = <&ccu RST_AHB1_SPI1>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                spi2: spi@1c6a000 {
@@ -1011,6 +1015,8 @@ spi2: spi@1c6a000 {
                        dma-names = "rx", "tx";
                        resets = <&ccu RST_AHB1_SPI2>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                spi3: spi@1c6b000 {
@@ -1023,6 +1029,8 @@ spi3: spi@1c6b000 {
                        dma-names = "rx", "tx";
                        resets = <&ccu RST_AHB1_SPI3>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                gic: interrupt-controller@1c81000 {