drm/i915: Fix bits vs. bytes mixup in dbuf block size computation

The spec used to say "8bpp" which someone took to mean 8 bytes per
pixel when in fact it was supposed to be 8 bits per pixel. The
spec has been updated to make it more clear now. Fix the code
to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181221171436.8218-4-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7473d6ea4bfe05f847a4bec1d1bae7f143791ac0..59e186b30d979d79370ffc26cf512fdef4bbc084 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4617,7 +4617,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
                                                             intel_pstate);
 
        if (INTEL_GEN(dev_priv) >= 11 &&
-           fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+           fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
                wp->dbuf_block_size = 256;
        else
                wp->dbuf_block_size = 512;