EDAC/altera: Add Stratix10 OCRAM ECC support

Use the newer ECC error injection method for Arria10 and Stratix10
OCRAM. If OCRAM has already been initialized during boot and OCRAM ECC
is enabled, ensure the Single Bit Error IRQ is enabled.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@kernel.org
Cc: James Morse <james.morse@arm.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: robh+dt@kernel.org
Link: https://lkml.kernel.org/r/1556030197-24534-2-git-send-email-thor.thayer@linux.intel.com

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 8816f74a22b4a8082804f72b2a168cf26d1e9506..b7bc8f020df8b4e2275809bd8d8cfbb26d5e3a69 100644 (file)
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1223,8 +1223,31 @@ static const struct edac_device_prv_data ocramecc_data = {
        .inject_fops = &altr_edac_device_inject_fops,
 };
 
+static int __maybe_unused
+altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
+{
+       void __iomem  *base = device->base;
+       int ret;
+
+       ret = altr_check_ecc_deps(device);
+       if (ret)
+               return ret;
+
+       /* Verify OCRAM has been initialized */
+       if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
+                          (base + ALTR_A10_ECC_INITSTAT_OFST)))
+               return -ENODEV;
+
+       /* Enable IRQ on Single Bit Error */
+       writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
+       /* Ensure all writes complete */
+       wmb();
+
+       return 0;
+}
+
 static const struct edac_device_prv_data a10_ocramecc_data = {
-       .setup = altr_check_ecc_deps,
+       .setup = altr_check_ocram_deps_init,
        .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
        .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
        .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
@@ -1234,7 +1257,7 @@ static const struct edac_device_prv_data a10_ocramecc_data = {
        .ue_set_mask = ALTR_A10_ECC_TDERRA,
        .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
        .ecc_irq_handler = altr_edac_a10_ecc_irq,
-       .inject_fops = &altr_edac_a10_device_inject_fops,
+       .inject_fops = &altr_edac_a10_device_inject2_fops,
        /*
         * OCRAM panic on uncorrectable error because sleep/resume
         * functions and FPGA contents are stored in OCRAM. Prefer