drm/vc4: Make sure to emit a tile coordinates between two MSAA loads.

The HW only executes a load once the tile coordinates packet happens,
and only tracks one at a time, so by emitting our two MSAA loads back
to back we would end up with an undefined color or Z buffer.

Fixes dEQP-EGL.functional.render.multi_context.gles2.rgb888_window

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190206232550.12012-1-eric@anholt.net

diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
index 273984f71ae284760a92252bef233329ce17ef55..3c918eeaf56eaa5362c839aa354cd9e66cb93351 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
@@ -148,6 +148,12 @@ static void emit_tile(struct vc4_exec_info *exec,
        }
 
        if (setup->zs_read) {
+               if (setup->color_read) {
+                       /* Exec previous load. */
+                       vc4_tile_coordinates(setup, x, y);
+                       vc4_store_before_load(setup);
+               }
+
                if (args->zs_read.flags &
                    VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
                        rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
@@ -156,12 +162,6 @@ static void emit_tile(struct vc4_exec_info *exec,
                                                    &args->zs_read, x, y) |
                                VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
                } else {
-                       if (setup->color_read) {
-                               /* Exec previous load. */
-                               vc4_tile_coordinates(setup, x, y);
-                               vc4_store_before_load(setup);
-                       }
-
                        rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
                        rcl_u16(setup, args->zs_read.bits);
                        rcl_u32(setup, setup->zs_read->paddr +
@@ -291,16 +291,15 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
                }
        }
        if (setup->zs_read) {
+               if (setup->color_read) {
+                       loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
+                       loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
+               }
+
                if (args->zs_read.flags &
                    VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
                        loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
                } else {
-                       if (setup->color_read &&
-                           !(args->color_read.flags &
-                             VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) {
-                               loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
-                               loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
-                       }
                        loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
                }
        }