]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
net: stmmac: setup higher frequency clk support for EHL & TGL
authorVoon Weifeng <weifeng.voon@intel.com>
Tue, 27 Aug 2019 01:38:11 +0000 (09:38 +0800)
committerDavid S. Miller <davem@davemloft.net>
Wed, 28 Aug 2019 04:59:38 +0000 (21:59 -0700)
EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk,
ptp clock and ptp_max_adj to 200MHz.

Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
include/linux/stmmac.h

index e969dc9bb9f03f76eabe72a3d8bb1445aaeda69e..20906287b6d465a921b5d2c886d6aeb4d82cdb46 100644 (file)
@@ -9,6 +9,7 @@
   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *******************************************************************************/
 
+#include <linux/clk-provider.h>
 #include <linux/pci.h>
 #include <linux/dmi.h>
 
@@ -174,6 +175,19 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
        plat->axi->axi_blen[1] = 8;
        plat->axi->axi_blen[2] = 16;
 
+       plat->ptp_max_adj = plat->clk_ptp_rate;
+
+       /* Set system clock */
+       plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
+                                                  "stmmac-clk", NULL, 0,
+                                                  plat->clk_ptp_rate);
+
+       if (IS_ERR(plat->stmmac_clk)) {
+               dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
+               plat->stmmac_clk = NULL;
+       }
+       clk_prepare_enable(plat->stmmac_clk);
+
        /* Set default value for multicast hash bins */
        plat->multicast_filter_bins = HASH_TABLE_SIZE;
 
@@ -193,6 +207,7 @@ static int ehl_common_data(struct pci_dev *pdev,
 
        plat->rx_queues_to_use = 8;
        plat->tx_queues_to_use = 8;
+       plat->clk_ptp_rate = 200000000;
        ret = intel_mgbe_common_data(pdev, plat);
        if (ret)
                return ret;
@@ -233,6 +248,7 @@ static int tgl_common_data(struct pci_dev *pdev,
 
        plat->rx_queues_to_use = 6;
        plat->tx_queues_to_use = 4;
+       plat->clk_ptp_rate = 200000000;
        ret = intel_mgbe_common_data(pdev, plat);
        if (ret)
                return ret;
@@ -438,10 +454,15 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
  */
 static void stmmac_pci_remove(struct pci_dev *pdev)
 {
+       struct net_device *ndev = dev_get_drvdata(&pdev->dev);
+       struct stmmac_priv *priv = netdev_priv(ndev);
        int i;
 
        stmmac_dvr_remove(&pdev->dev);
 
+       if (priv->plat->stmmac_clk)
+               clk_unregister_fixed_rate(priv->plat->stmmac_clk);
+
        for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
                if (pci_resource_len(pdev, i) == 0)
                        continue;
index c48224973a374577a1d196ac71ffed1d25f776d3..173493db038c0a9f5199bf1675429e0b379a6b4f 100644 (file)
@@ -194,6 +194,9 @@ void stmmac_ptp_register(struct stmmac_priv *priv)
                priv->pps[i].available = true;
        }
 
+       if (priv->plat->ptp_max_adj)
+               stmmac_ptp_clock_ops.max_adj = priv->plat->ptp_max_adj;
+
        stmmac_ptp_clock_ops.n_per_out = priv->dma_cap.pps_out_num;
 
        spin_lock_init(&priv->ptp_lock);
index 5cc6b6faf35913924aea4950aefd2a8a75262bcc..7ad7ae35cf88a884815aeea662c241dff8106f8c 100644 (file)
@@ -168,6 +168,7 @@ struct plat_stmmacenet_data {
        struct clk *clk_ptp_ref;
        unsigned int clk_ptp_rate;
        unsigned int clk_ref_rate;
+       s32 ptp_max_adj;
        struct reset_control *stmmac_rst;
        struct stmmac_axi *axi;
        int has_gmac4;