drm/amd/powerplay: skip soc clk setting under pp one vf

Under sriov pp one vf mode, there is no need to set
soc clk under pp one vf because smu firmware will depend
on the mclk to set the appropriate soc clk for it.

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by : Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 148446570e21362d5f666551f582618e922f54b7..92a65e3daff4bd7405ed6c6e06775c45d99a1968 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
        if (!data->registry_data.mclk_dpm_key_disabled) {
                if (data->smc_state_table.mem_boot_level !=
                                data->dpm_table.mem_table.dpm_state.soft_min_level) {
-                       if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
+                       if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
+                           && hwmgr->not_vf) {
                                socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
                                smum_send_msg_to_smc_with_parameter(hwmgr,
                                                PPSMC_MSG_SetSoftMinSocclkByIndex,