powerpc/perf: Fix incorrect event codes in power9-event-list

These have been changed in the hardware, update Linux's version.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/power9-events-list.h b/arch/powerpc/perf/power9-events-list.h
index cda6fcb809ca25a9d10d9968c6798d16564bbd14..6447dc1c3d896cea18615d3b5bacc4bb6285fbb1 100644 (file)
--- a/arch/powerpc/perf/power9-events-list.h
+++ b/arch/powerpc/perf/power9-events-list.h
@@ -34,15 +34,15 @@ EVENT(PM_L1_ICACHE_MISS,                    0x200fd)
 /* Instruction Demand sectors wriittent into IL1 */
 EVENT(PM_L1_DEMAND_WRITE,                      0x0408c)
 /* Instruction prefetch written into IL1 */
-EVENT(PM_IC_PREF_WRITE,                                0x0408e)
+EVENT(PM_IC_PREF_WRITE,                                0x0488c)
 /* The data cache was reloaded from local core's L3 due to a demand load */
 EVENT(PM_DATA_FROM_L3,                         0x4c042)
 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
 EVENT(PM_DATA_FROM_L3MISS,                     0x300fe)
 /* All successful D-side store dispatches for this thread */
-EVENT(PM_L2_ST,                                        0x16081)
+EVENT(PM_L2_ST,                                        0x16880)
 /* All successful D-side store dispatches for this thread that were L2 Miss */
-EVENT(PM_L2_ST_MISS,                           0x26081)
+EVENT(PM_L2_ST_MISS,                           0x26880)
 /* Total HW L3 prefetches(Load+store) */
 EVENT(PM_L3_PREF_ALL,                          0x4e052)
 /* Data PTEG reload */