]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
Merge tag 'intel-gpio-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy...
authorLinus Walleij <linus.walleij@linaro.org>
Wed, 13 Nov 2019 22:03:23 +0000 (23:03 +0100)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 13 Nov 2019 22:03:23 +0000 (23:03 +0100)
intel-gpio for v5.5-1

* Prerequisite patch against GPIO library to register pin ranges in time.
* Second attempt to fix Intel Merrifield GPIO driver to utilize irqchip.

The following is an automated git shortlog grouped by driver:

gpiolib:
 -  Introduce ->add_pin_ranges() callback

merrifield:
 -  Pass irqchip when adding gpiochip
 -  Add GPIO <-> pin mapping ranges via callback

drivers/gpio/gpio-merrifield.c
drivers/gpio/gpiolib.c
include/linux/gpio/driver.h

index 0ee29c2049be01fd147ff1356ee39d7afc57a6cb..48918a016cd8310f97fc33232a5001646a178b3f 100644 (file)
@@ -365,8 +365,9 @@ static void mrfld_irq_handler(struct irq_desc *desc)
        chained_irq_exit(irqchip, desc);
 }
 
-static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
+static int mrfld_irq_init_hw(struct gpio_chip *chip)
 {
+       struct mrfld_gpio *priv = gpiochip_get_data(chip);
        void __iomem *reg;
        unsigned int base;
 
@@ -378,6 +379,8 @@ static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
                reg = gpio_reg(&priv->chip, base, GFER);
                writel(0, reg);
        }
+
+       return 0;
 }
 
 static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
@@ -396,14 +399,36 @@ static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
        return name;
 }
 
-static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
 {
+       struct mrfld_gpio *priv = gpiochip_get_data(chip);
        const struct mrfld_gpio_pinrange *range;
        const char *pinctrl_dev_name;
+       unsigned int i;
+       int retval;
+
+       pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
+       for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
+               range = &mrfld_gpio_ranges[i];
+               retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
+                                               range->gpio_base,
+                                               range->pin_base,
+                                               range->npins);
+               if (retval) {
+                       dev_err(priv->dev, "failed to add GPIO pin range\n");
+                       return retval;
+               }
+       }
+
+       return 0;
+}
+
+static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+       struct gpio_irq_chip *girq;
        struct mrfld_gpio *priv;
        u32 gpio_base, irq_base;
        void __iomem *base;
-       unsigned int i;
        int retval;
 
        retval = pcim_enable_device(pdev);
@@ -444,42 +469,31 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
        priv->chip.base = gpio_base;
        priv->chip.ngpio = MRFLD_NGPIO;
        priv->chip.can_sleep = false;
+       priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
 
        raw_spin_lock_init(&priv->lock);
 
-       pci_set_drvdata(pdev, priv);
+       girq = &priv->chip.irq;
+       girq->chip = &mrfld_irqchip;
+       girq->init_hw = mrfld_irq_init_hw;
+       girq->parent_handler = mrfld_irq_handler;
+       girq->num_parents = 1;
+       girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
+                                    sizeof(*girq->parents), GFP_KERNEL);
+       if (!girq->parents)
+               return -ENOMEM;
+       girq->parents[0] = pdev->irq;
+       girq->first = irq_base;
+       girq->default_type = IRQ_TYPE_NONE;
+       girq->handler = handle_bad_irq;
+
        retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
        if (retval) {
                dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
                return retval;
        }
 
-       pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
-       for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
-               range = &mrfld_gpio_ranges[i];
-               retval = gpiochip_add_pin_range(&priv->chip,
-                                               pinctrl_dev_name,
-                                               range->gpio_base,
-                                               range->pin_base,
-                                               range->npins);
-               if (retval) {
-                       dev_err(&pdev->dev, "failed to add GPIO pin range\n");
-                       return retval;
-               }
-       }
-
-       retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
-                                     handle_bad_irq, IRQ_TYPE_NONE);
-       if (retval) {
-               dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
-               return retval;
-       }
-
-       mrfld_irq_init_hw(priv);
-
-       gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
-                                    mrfld_irq_handler);
-
+       pci_set_drvdata(pdev, priv);
        return 0;
 }
 
index dba5f08f308c47ecf53c07cd3101aa8dad65212e..8fdde922786bdcfdc6283f514d8928bc1ac7df62 100644 (file)
@@ -390,6 +390,14 @@ static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip)
        gpiochip->valid_mask = NULL;
 }
 
+static int gpiochip_add_pin_ranges(struct gpio_chip *gc)
+{
+       if (gc->add_pin_ranges)
+               return gc->add_pin_ranges(gc);
+
+       return 0;
+}
+
 bool gpiochip_line_is_valid(const struct gpio_chip *gpiochip,
                                unsigned int offset)
 {
@@ -1520,6 +1528,10 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
                }
        }
 
+       ret = gpiochip_add_pin_ranges(chip);
+       if (ret)
+               goto err_remove_of_chip;
+
        acpi_gpiochip_add(chip);
 
        machine_gpiochip_add(chip);
index cc9ade4552d95c9de2b8c929e66f06ab875e799b..e2480ef94c5597b5cb8a33dcafec95e4c29d10b0 100644 (file)
@@ -289,6 +289,9 @@ struct gpio_irq_chip {
  *     state (such as pullup/pulldown configuration).
  * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
  *     not all GPIOs are valid.
+ * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
+ *     requires special mapping of the pins that provides GPIO functionality.
+ *     It is called after adding GPIO chip and before adding IRQ chip.
  * @base: identifies the first GPIO number handled by this chip;
  *     or, if negative during registration, requests dynamic ID allocation.
  *     DEPRECATION: providing anything non-negative and nailing the base
@@ -379,6 +382,8 @@ struct gpio_chip {
                                                   unsigned long *valid_mask,
                                                   unsigned int ngpios);
 
+       int                     (*add_pin_ranges)(struct gpio_chip *chip);
+
        int                     base;
        u16                     ngpio;
        const char              *const *names;