RISC-V: Typo fixes in image header and documentation.

There are some typos in boot image header and riscv boot documentation.

Fix the typos.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Link: https://lore.kernel.org/r/20191009010637.9955-1-atish.patra@wdc.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst
index 518d46d2389dbe1013570a89519c6dc00ac4e225..d7752533865ff9a0a24c7b85034282169a23019d 100644 (file)
--- a/Documentation/riscv/boot-image-header.rst
+++ b/Documentation/riscv/boot-image-header.rst
@@ -22,7 +22,7 @@ The following 64-byte header is present in decompressed Linux kernel image::
        u64 res2 = 0;             /* Reserved */
        u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
        u32 magic2 = 0x05435352;  /* Magic number 2, little endian, "RSC\x05" */
-       u32 res4;                 /* Reserved for PE COFF offset */
+       u32 res3;                 /* Reserved for PE COFF offset */
 
 This header format is compliant with PE/COFF header and largely inspired from
 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
@@ -34,7 +34,7 @@ Notes
 - This header can also be reused to support EFI stub for RISC-V in future. EFI
   specification needs PE/COFF image header in the beginning of the kernel image
   in order to load it as an EFI application. In order to support EFI stub,
-  code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should
+  code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should
   point to the rest of the PE/COFF header.
 
 - version field indicate header version number

diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
index 7b0f92ba0acc4f7541fe130f1a7b82da21444c37..e0b319af3681a6bdf42ed49504b95e1b873122b8 100644 (file)
--- a/arch/riscv/include/asm/image.h
+++ b/arch/riscv/include/asm/image.h
@@ -42,7 +42,7 @@
  * @res2:              reserved
  * @magic:             Magic number (RISC-V specific; deprecated)
  * @magic2:            Magic number 2 (to match the ARM64 'magic' field pos)
- * @res4:              reserved (will be used for PE COFF offset)
+ * @res3:              reserved (will be used for PE COFF offset)
  *
  * The intention is for this header format to be shared between multiple
  * architectures to avoid a proliferation of image header formats.
@@ -59,7 +59,7 @@ struct riscv_image_header {
        u64 res2;
        u64 magic;
        u32 magic2;
-       u32 res4;
+       u32 res3;
 };
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_RISCV_IMAGE_H */