]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: STi: Add fake reg property for usb2_picophyX nodes
authorPatrice Chotard <patrice.chotard@st.com>
Fri, 19 Jan 2018 10:18:19 +0000 (11:18 +0100)
committerPatrice Chotard <patrice.chotard@st.com>
Mon, 12 Feb 2018 14:24:38 +0000 (15:24 +0100)
Add fake reg property for usb2_picophy nodes.
This allows to fix the following warning when compiling dtb
with W=1 option :

arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih410-b2120.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy2 missing or empty reg/ranges property
arch/arm/boot/dts/stih418-b2199.dtb: Warning (simple_bus_reg):
Node /soc/phy3 missing or empty reg/ranges property

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
arch/arm/boot/dts/stih407-family.dtsi
arch/arm/boot/dts/stih410-b2120.dts
arch/arm/boot/dts/stih410-b2260.dts
arch/arm/boot/dts/stih410.dtsi
arch/arm/boot/dts/stih418.dtsi

index 00a3838236d1901e9f420b72dc3d9081a2960a2e..5df827b00eb6b61d453650f0e1ee8aef697025d0 100644 (file)
@@ -385,8 +385,9 @@ i2c@9541000 {
                        status = "disabled";
                };
 
-               usb2_picophy0: phy1 {
+               usb2_picophy0: phy1@0 {
                        compatible = "st,stih407-usb2-phy";
+                       reg = <0 0>;
                        #phy-cells = <0>;
                        st,syscfg = <&syscfg_core 0x100 0xf4>;
                        resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
index 23199b1b09914e20e524eac8fe303220dc3ff454..d1d908b9e34c4489eb073964d16379e486ebe17d 100644 (file)
@@ -37,11 +37,11 @@ mmc0: sdhci@9060000 {
                        sd-uhs-ddr50;
                };
 
-               usb2_picophy1: phy2 {
+               usb2_picophy1: phy2@0 {
                        status = "okay";
                };
 
-               usb2_picophy2: phy3 {
+               usb2_picophy2: phy3@0 {
                        status = "okay";
                };
 
index cea5c840ca9f61aace908caa65d04932d30fdc18..8bcd58118dba7f0eb54e2bf1f8b80a31ccc6cd2e 100644 (file)
@@ -127,11 +127,11 @@ pwm1: pwm@9510000 {
                        status = "okay";
                };
 
-               usb2_picophy1: phy2 {
+               usb2_picophy1: phy2@0 {
                        status = "okay";
                };
 
-               usb2_picophy2: phy3 {
+               usb2_picophy2: phy3@0 {
                        status = "okay";
                };
 
index 815df2f7c1036d633f412b3f19af5109f1ac9eeb..bfbc73743b29c96a7016b0d90ad0d889fcdfb5c1 100644 (file)
@@ -16,8 +16,9 @@ aliases {
        };
 
        soc {
-               usb2_picophy1: phy2 {
+               usb2_picophy1: phy2@0 {
                        compatible = "st,stih407-usb2-phy";
+                       reg = <0 0>;
                        #phy-cells = <0>;
                        st,syscfg = <&syscfg_core 0xf8 0xf4>;
                        resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -27,8 +28,9 @@ usb2_picophy1: phy2 {
                        status = "disabled";
                };
 
-               usb2_picophy2: phy3 {
+               usb2_picophy2: phy3@0 {
                        compatible = "st,stih407-usb2-phy";
+                       reg = <0 0>;
                        #phy-cells = <0>;
                        st,syscfg = <&syscfg_core 0xfc 0xf4>;
                        resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
index e6525ab4d9bb6d9c6ae87513e861b3846b3109eb..0efb3cd6a86e9c5a4a5ba09d24f5490d55c66b46 100644 (file)
@@ -30,8 +30,9 @@ cpu@3 {
        };
 
        soc {
-               usb2_picophy1: phy2 {
+               usb2_picophy1: phy2@0 {
                        compatible = "st,stih407-usb2-phy";
+                       reg = <0 0>;
                        #phy-cells = <0>;
                        st,syscfg = <&syscfg_core 0xf8 0xf4>;
                        resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -39,8 +40,9 @@ usb2_picophy1: phy2 {
                        reset-names = "global", "port";
                };
 
-               usb2_picophy2: phy3 {
+               usb2_picophy2: phy3@0 {
                        compatible = "st,stih407-usb2-phy";
+                       reg = <0 0>;
                        #phy-cells = <0>;
                        st,syscfg = <&syscfg_core 0xfc 0xf4>;
                        resets = <&softreset STIH407_PICOPHY_SOFTRESET>,