ARM64: dts: meson-gx: Add missing L2 cache node

In order to remove the boot warning :
[    2.290933] Unable to detect cache hierarchy from DT for CPU 0
And add missing L2 cache hierarchy information, add a simple l2 cache node
and reference it from the A53 cpu nodes.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 0737056b369f105cdda1177ddeb7a97633034850..a6cd953ef7e17864219ca8ed40ef3718456d81fa 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -64,6 +64,7 @@ cpu0: cpu@0 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       next-level-cache = <&l2>;
                };
 
                cpu1: cpu@1 {
@@ -71,6 +72,7 @@ cpu1: cpu@1 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       next-level-cache = <&l2>;
                };
 
                cpu2: cpu@2 {
@@ -78,6 +80,7 @@ cpu2: cpu@2 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       next-level-cache = <&l2>;
                };
 
                cpu3: cpu@3 {
@@ -85,6 +88,11 @@ cpu3: cpu@3 {
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       next-level-cache = <&l2>;
+               };
+
+               l2: l2-cache0 {
+                       compatible = "cache";
                };
        };