ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE

Cosmetic change of integer value "0" in the third field of the
"interrupts" property to the correct named constant.

Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index c7198900b42626e50fae284264139418c25f53c9..1e54113d6d9ac56440b0f49dc88e7c955d905ef1 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -586,7 +586,7 @@ rpm_msg_ram: memory@fc428000 {
                blsp1_uart1: serial@f991d000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0xf991d000 0x1000>;
-                       interrupts = <GIC_SPI 107 0x0>;
+                       interrupts = <GIC_SPI 107 IRQ_TYPE_NONE>;
                        clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        status = "disabled";
@@ -595,7 +595,7 @@ blsp1_uart1: serial@f991d000 {
                blsp1_uart2: serial@f991e000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0xf991e000 0x1000>;
-                       interrupts = <GIC_SPI 108 0x0>;
+                       interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
                        clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        status = "disabled";
@@ -605,8 +605,8 @@ sdhci@f9824900 {
                        compatible = "qcom,sdhci-msm-v4";
                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                        reg-names = "hc_mem", "core_mem";
-                       interrupts = <GIC_SPI 123 0>,
-                                    <GIC_SPI 138 0>;
+                       interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
+                                    <GIC_SPI 138 IRQ_TYPE_NONE>;
                        interrupt-names = "hc_irq", "pwr_irq";
                        clocks = <&gcc GCC_SDCC1_APPS_CLK>,
                                 <&gcc GCC_SDCC1_AHB_CLK>,
@@ -633,8 +633,8 @@ sdhci@f98a4900 {
                        compatible = "qcom,sdhci-msm-v4";
                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
                        reg-names = "hc_mem", "core_mem";
-                       interrupts = <GIC_SPI 125 0>,
-                                    <GIC_SPI 221 0>;
+                       interrupts = <GIC_SPI 125 IRQ_TYPE_NONE>,
+                                    <GIC_SPI 221 IRQ_TYPE_NONE>;
                        interrupt-names = "hc_irq", "pwr_irq";
                        clocks = <&gcc GCC_SDCC2_APPS_CLK>,
                                 <&gcc GCC_SDCC2_AHB_CLK>,
@@ -701,7 +701,7 @@ msmgpio: pinctrl@fd510000 {
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
-                       interrupts = <GIC_SPI 208 0>;
+                       interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
                };
 
                i2c@f9924000 {
@@ -746,7 +746,7 @@ spmi_bus: spmi@fc4cf000 {
                              <0xfc4cb000 0x1000>,
                              <0xfc4ca000 0x1000>;
                        interrupt-names = "periph_irq";
-                       interrupts = <GIC_SPI 190 0>;
+                       interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
                        qcom,ee = <0>;
                        qcom,channel = <0>;
                        #address-cells = <2>;