ARM: dts: r8a7744: Add PCIe Controller device node

Add a device node for the PCIe controller on the Renesas
RZ/G1N (r8a7744) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 33e15c5f21c9c5614b4fbf3066deb788ed91e5cb..04148d608fc4bbc09b0b52080ab9e7ee13edccd9 100644 (file)
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -1616,6 +1616,34 @@ vsp@fe938000 {
                        resets = <&cpg 127>;
                };
 
+               pciec: pcie@fe000000 {
+                       compatible = "renesas,pcie-r8a7744",
+                                    "renesas,pcie-rcar-gen2";
+                       reg = <0 0xfe000000 0 0x80000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       bus-range = <0x00 0xff>;
+                       device_type = "pci";
+                       ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+                                 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+                                 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+                                 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+                       /* Map all possible DDR as inbound ranges */
+                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+                                     0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+                       interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0>;
+                       interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                       clock-names = "pcie", "pcie_bus";
+                       power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+                       resets = <&cpg 319>;
+                       status = "disabled";
+               };
+
                du: display@feb00000 {
                        reg = <0 0xfeb00000 0 0x40000>,
                              <0 0xfeb90000 0 0x1c>;