context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
(ddr4_dram_factor_single_Channel * v->number_of_channels));
- if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
+ if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
- }
context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
dc->debug.min_disp_clk_khz;
}
- context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
+ context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
+ v->dispclk_dppclk_ratio;
context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
switch (v->voltage_level) {
case 0:
/* pipe not split previously needs split */
hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
ASSERT(hsplit_pipe);
- split_stream_across_pipes(
- &context->res_ctx, pool,
- pipe, hsplit_pipe);
+ split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
}
dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
}
if (v->voltage_level == 0) {
-
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
dc->dcn_soc->sr_enter_plus_exit_time;
context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
int i;
/* recalculate DML parameters */
- if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
+ if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
return false;
- }
/* apply updated bandwidth parameters */
dc->hwss.prepare_bandwidth(dc, context);
}
#endif
-bool dcn20_validate_bandwidth(struct dc *dc,
- struct dc_state *context,
- bool fast_validate)
+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
+ bool fast_validate)
{
+ bool out = false;
+
int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
int pipe_split_from[MAX_PIPES];
bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
}
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
- if (!pipe_cnt)
- goto validate_pass;
+
+ if (!pipe_cnt) {
+ out = true;
+ goto validate_out;
+ }
context->bw_ctx.dml.ip.odm_capable = 0;
+
vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
+
context->bw_ctx.dml.ip.odm_capable = odm_capable;
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
}
#endif
+ if (fast_validate) {
+ out = true;
+ goto validate_out;
+ }
+
for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
pipe_idx,
cstate_en,
context->bw_ctx.bw.dcn.clk.p_state_change_support);
+
context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
&context->res_ctx.pipe_ctx[i].rq_regs,
pipes[pipe_idx].pipe);
+
pipe_idx++;
}
-validate_pass:
- kfree(pipes);
- return true;
+ out = true;
+ goto validate_out;
validate_fail:
DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
+
+ out = false;
+
+validate_out:
kfree(pipes);
- return false;
+
+ return out;
}
struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(