]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings: Document the Synopsys DW AXI DMA bindings
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Tue, 6 Mar 2018 11:46:15 +0000 (14:46 +0300)
committerVinod Koul <vinod.koul@intel.com>
Mon, 19 Mar 2018 08:08:20 +0000 (13:38 +0530)
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
new file mode 100644 (file)
index 0000000..f237b79
--- /dev/null
@@ -0,0 +1,41 @@
+Synopsys DesignWare AXI DMA Controller
+
+Required properties:
+- compatible: "snps,axi-dma-1.01a"
+- reg: Address range of the DMAC registers. This should include
+  all of the per-channel registers.
+- interrupt: Should contain the DMAC interrupt number.
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device.
+- dma-channels: Number of channels supported by hardware.
+- snps,dma-masters: Number of AXI masters supported by the hardware.
+- snps,data-width: Maximum AXI data width supported by hardware.
+  (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+- snps,priority: Priority of channel. Array size is equal to the number of
+  dma-channels. Priority value must be programmed within [0:dma-channels-1]
+  range. (0 - minimum priority)
+- snps,block-size: Maximum block size supported by the controller channel.
+  Array size is equal to the number of dma-channels.
+
+Optional properties:
+- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
+  in this property. If this property is missing the maximum AXI burst length
+  supported by DMAC is used. [1:256]
+
+Example:
+
+dmac: dma-controller@80000 {
+       compatible = "snps,axi-dma-1.01a";
+       reg = <0x80000 0x400>;
+       clocks = <&core_clk>, <&cfgr_clk>;
+       clock-names = "core-clk", "cfgr-clk";
+       interrupt-parent = <&intc>;
+       interrupts = <27>;
+
+       dma-channels = <4>;
+       snps,dma-masters = <2>;
+       snps,data-width = <3>;
+       snps,block-size = <4096 4096 4096 4096>;
+       snps,priority = <0 1 2 3>;
+       snps,axi-max-burst-len = <16>;
+};