]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: meson: g12a: add mdio multiplexer
authorJerome Brunet <jbrunet@baylibre.com>
Mon, 20 May 2019 13:13:59 +0000 (15:13 +0200)
committerKevin Hilman <khilman@baylibre.com>
Tue, 11 Jun 2019 22:50:01 +0000 (15:50 -0700)
Add the g12a mdio multiplexer which allows to connect to either
an external phy through the SoC pins or the internal 10/100 phy

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

index def02ebf650198fd98e3ec4cc98e0f0ef6213371..90da7cc81681e11013ee076670cdc75d9154001f 100644 (file)
@@ -1698,6 +1698,38 @@ usb3_pcie_phy: phy@46000 {
                                assigned-clock-rates = <100000000>;
                                #phy-cells = <1>;
                        };
+
+                       eth_phy: mdio-multiplexer@4c000 {
+                               compatible = "amlogic,g12a-mdio-mux";
+                               reg = <0x0 0x4c000 0x0 0xa4>;
+                               clocks = <&clkc CLKID_ETH_PHY>,
+                                        <&xtal>,
+                                        <&clkc CLKID_MPLL_50M>;
+                               clock-names = "pclk", "clkin0", "clkin1";
+                               mdio-parent-bus = <&mdio0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               ext_mdio: mdio@0 {
+                                       reg = <0>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+
+                               int_mdio: mdio@1 {
+                                       reg = <1>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       internal_ephy: ethernet_phy@8 {
+                                               compatible = "ethernet-phy-id0180.3301",
+                                                            "ethernet-phy-ieee802.3-c22";
+                                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                                               reg = <8>;
+                                               max-speed = <100>;
+                                       };
+                               };
+                       };
                };
 
                aobus: bus@ff800000 {