MIPS: BCM63XX: Use the Chip ID register for identifying the SoC

Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the
revision bits. But since they all have the Chip ID register at the same
location, we can use that to identify the SoC we are running on.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: Maxime Bizon <mbizon@freebox.fr>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Kevin Cernekee <cernekee@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3955/
Reviewed-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 8f0d6c7725ea278eecf0fedca355fb5e33c7e824..e3c1da59ea13a9ad005eb7c86b79b1238a3b380c 100644 (file)
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -228,17 +228,21 @@ void __init bcm63xx_cpu_init(void)
                bcm63xx_irqs = bcm6345_irqs;
                break;
        case CPU_BMIPS4350:
-               switch (read_c0_prid() & 0xf0) {
-               case 0x10:
+               if ((read_c0_prid() & 0xf0) == 0x10) {
                        expected_cpu_id = BCM6358_CPU_ID;
                        bcm63xx_regs_base = bcm6358_regs_base;
                        bcm63xx_irqs = bcm6358_irqs;
-                       break;
-               case 0x30:
-                       expected_cpu_id = BCM6368_CPU_ID;
-                       bcm63xx_regs_base = bcm6368_regs_base;
-                       bcm63xx_irqs = bcm6368_irqs;
-                       break;
+               } else {
+                       /* all newer chips have the same chip id location */
+                       u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
+
+                       switch (chip_id) {
+                       case BCM6368_CPU_ID:
+                               expected_cpu_id = BCM6368_CPU_ID;
+                               bcm63xx_regs_base = bcm6368_regs_base;
+                               bcm63xx_irqs = bcm6368_irqs;
+                               break;
+                       }
                }
                break;
        }